Mentor Graphics PADS 9.0 Flow
PADS 9.0 flow, from Mentor Graphics, features new levels of functionality, scalability, and integration. PADS design solution helps individuals and design teams to develop PCBs within a highly productive and easy-to-use environment. PADS enables engineers to accomplish a wide breadth and depth of core PCB development tasks — including schematic entry, analog design, signal and [...]
STMicroelectronics ESL SoC Reference Design Flow
STMicroelectronics (NYSE: STM) recently announced a certified electronic system level (ESL) System-on-Chip reference design flow. Aimed at complex designs for next-generation consumer electronics equipment, ST’s integrated ESL reference-design flow for complex digital CMOS designs combines high-level synthesis, sequential equivalence checking, power exploration and lint checkers that look for errors in code construction, thereby providing a [...]
TSMC Reference Flow 9.0
Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) recently announced Reference Flow 9.0. The latest version of TSMC’s design methodology lowers design obstacles, improves design margins, and increases yields of its 40nm process technology. Reference Flow 9.0 addresses new design challenges of TSMC’s advanced technologies up to and including 40nm process technology, with features [...]
IMEC Variability Aware Modeling Flow for Sub-45nm
IMEC recently announced a variability-aware modeling (VAM) flow that analyzes process variability of sub-45nm technologies which enables designers to optimize their system design for timing, energy and yield versus expected application load. The flow assesses the impact of process variations and degradation effects of sub-45nm technologies on the system performance by giving valuable information to [...]
Synopsys-SMIC RTL-to-GDSII 90nm Design Flow
Synopsys, Inc. (NASDAQ: SNPS) and Semiconductor Manufacturing International Corporation (SMIC) (NYSE: SMI)(SEHK: 0981.HK) recently released an enhanced 90 nanometer (nm) hierarchical, multi-voltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test (DFT) and design-for-manufacturing (DFM) capabilities. Key features of the reference flow include topographical synthesis in the Design Compiler(tm) Ultra product, scan compression in [...]
Low Power Coalition’s Common Power Format Roadmap
Silicon Integration Initiative (Si2) recently published the Low Power Coalition’s (LPC) roadmap for Common Power Format (CPF) extensions planned out through mid-2009. Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and [...]
Cadence ARM11, ARM1176JZF-S Reference Methodologies
Cadence Design Systems, Inc. (NASDAQ: CDNS) and ARM [(LSE: ARM); (NASDAQ: ARMHY) created implementation reference methodologies for the ARM11(TM) MPCore(TM) multicore processor and the ARM1176JZF-S(TM) processor. The Cadence reference methodologies for the two ARM processors provide enhanced design solutions for designing multicore, low-power devices.
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