Nanometer IC Variation Analysis Design Flow
Berkeley Design Automatio and Solido Design Automation teamm on a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. In the solution, Variation Designer utilizes the AFS Platform. The result is variation analysis capabilities that enable designers to rapidly reduce variation risk.
Calypto Design Systems PowerAdviser Flow
Calypto Design Systems introduced a new PowerAdviser Flow. The new flow enables designers to deliver power-optimized SoC designs. Using sequential design information generated by Calypto’s PowerPro CG and PowerPro MG tools, the PowerAdviser Flow provides users with specific design changes that can be manually implemented in their RTL code to reduce power.
SMIC-Cadence 65nm Low Power Reference Flow 4.0
Cadence Design Systems introduced a comprehensive low-power design flow for engineers targeting the 65-nanometer process at Semiconductor Manufacturing International Corporation (SMIC). Based on the Cadence Low-Power Solution, the flow enables faster design of leading-edge, low-power semiconductors using a single, comprehensive design platform. The SMIC-Cadence Reference Flow 4.0 addresses the need for power-efficient design innovation with [...]
Calypto Sequential Optimization Flow
Calypto Design Systems unveiled a fully automated design flow for advancing the delivery of optimized, high-performance IP blocks for SoC designs. The Sequential Optimization Flow features Calypto’s SLEC RTL tool and new analysis capabilities of the PowerPro CG (clock gating) tool. With Calypto’s Sequential Optimization Flow, designers can use a fully automated flow to optimize [...]
Magma Talus-based Low-Power Reference Flow for SMIC 65nm Processes
Magma Design Automation unveiled a low-power Talus-based IC implementation reference flow for the 65-nanometer process and low-leakage-process intellectual property (IP) from Semiconductor Manufacturing International Corporation (SMIC). Talus enables designers to address power considerations throughout the flow and within a single environment. Using Talus, SMIC customers can get the best combination of performance, low power and [...]
Mentor Graphics Expanded Solution for TSMC Reference Flow 10.0
Mentor Graphics has expanded their set of tools and technologies included in the TSMC Reference Flow 10.0. The expanded Mentor track supports advanced functional verification for complex ICs, netlist-to-GDSII implementation for 28nm ICs, tighter integration with the ubiquitous Calibre physical verification and DFM platform, and tools for layout aware test failure diagnosis. The improved Mentor [...]
Catapult-SpyGlass ESL-to-RTL Power Optimization Flow
Atrenta and Mentor Graphics teamed together on an high-level synthesis power optimization flow. The collaboration between the two companies has resulted in an interface between Mentor’s Catapult C Synthesis high-level synthesis tool and Atrenta’s SpyGlass-Power RTL power estimation and reduction tool to automate multi-level clock gating. The RTL output from Catapult is seamlessly handed off [...]
1Team Genesis Reference Flow for Automated SoC Assembly
Atrenta, Sonics, and Denali Software are building a reference flow based on Atrenta’s 1Team-Genesis automated chip assembly product. The flow will facilitate a healthy eco-system of semiconductor intellectual property (IP) that is qualified and ready to use in automated system-on-chip (SoC) assembly. The collaboration enables IP suppliers to ensure seamless integration of their IP portfolio [...]
SMIC and Synopsys Reference Flow 4.0
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) introduced version 4.0 of their 65-nanometer (nm) RTL-to-GDSII reference design flow. The reference flow features support for the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology. The joint solution gives IC engineering teams a proven reference flow to advance SoC designs targeting SMIC’s 65nm process technology [...]
Interconnect and Memory Subsystem Performance Optimization Design Flow
CoWare unveiled the Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect. The new design flow enables early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM AMBA-based virtual platforms. CoWare Platform Architect tool and IP model enhancements and CoWare CoStart services are available immediately for use with the 2009.1.1 release.
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