Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.
Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.
Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.
Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire chip flow holistically. It supports Cadence’s approach to Silicon Realization, which is a key element of the EDA360 vision. The new flow is available now.
Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.
Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s 32/28-nm process technology.
Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.
Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.
Altos Design Automation and Extreme DA developed a signal-integrity (SI) design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below. Extreme DA GoldTime for use with Altos Variety and Liberate models is available now from Extreme DA. Pricing varies depending on configuration. Altos Variety and Liberate approved libraries for Extreme DA GoldTime are available now from Altos.
Berkeley Design Automatio and Solido Design Automation teamm on a validated flow for rapid reduction in variation risk in nanometer designs at the transistor level. In the solution, Variation Designer utilizes the AFS Platform. The result is variation analysis capabilities that enable designers to rapidly reduce variation risk.