EDA Blog » Design Flow

SMIC 40nm Reference Flow Features Cadence Encounter Digital Technology

Ken Cheung — Tue, 10 Apr 2012 16:02:21 +0000

Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.

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Cadence Releases New RTL-to-GDSII Flow for Giga-Scale, 20nm Designs

Ken Cheung — Mon, 05 Mar 2012 17:23:25 +0000

Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.

Cadence, Samsung Foundry Develop DFM Flows for 32nm, 28nm, 20nm Chip Design

Ken Cheung — Mon, 06 Feb 2012 19:08:51 +0000

Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.

Cadence and GLOBALFOUNDRIES In-Design DRC+ Verification Flow

Ken Cheung — Mon, 29 Aug 2011 17:37:03 +0000

Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of complex chip designs headed for manufacturing.

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Synopsys 28nm Design Solutions for TSMC Reference Flow 12.0

Ken Cheung — Fri, 27 May 2011 16:08:32 +0000

Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.

Arteris and EVE Design Flow for System-on-Chip Development

Ken Cheung — Mon, 14 Mar 2011 06:59:06 +0000

Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.

Cadence Digital End-to-end Flow for 28nm Giga-gate/Gigahertz Designs

Ken Cheung — Mon, 31 Jan 2011 17:59:42 +0000

Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire chip flow holistically. It supports Cadence’s approach to Silicon Realization, which is a key element of the EDA360 vision. The new flow is available now.

RTL-to-GDSII Silicon Realization Reference Flow for Common Platform

Ken Cheung — Mon, 17 Jan 2011 19:51:28 +0000

Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and Encounter Power System.

Magma Reference Flow for Common Platform 32/28nm Low-Power Process

Ken Cheung — Mon, 17 Jan 2011 18:08:24 +0000

Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process libraries and the Common Platform alliance’s 32/28-nm process technology.

Mentor Graphics and Dongbu HiTek Technology Design Kits for Analog BCDMOS

Ken Cheung — Mon, 10 Jan 2011 18:51:14 +0000

Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.