Category Archives: Design Flow

Synopsys Debuts Galaxy Implementation for TSMC 16nm FinFET Reference Flow

Synopsys introduced a comprehensive design implementation solution for TSMC’s 16-nanometer (nm) FinFET reference flow. The jointly developed reference flow is built on tool certification currently in TSMC’s V0.5 Design Rule Manual (DRM) and SPICE. The collaboration between the two companies has resulted in a comprehensive FinFET implementation flow that can be deployed for production use by mutual customers.

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Mentor Graphics Debuts IP to System, UPF Low-power Verification Flow

Mentor Graphics introduced a comprehensive IP to System, UPF-based low-power verification flow. Mentor now has platform-level support of Unified Power Format in both the Questa functional verification platform and the Veloce family of hardware emulators that lets users create a single specification for power intent that is reusable and consistent, and facilitates low-power verification across simulation, formal and emulation.

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AWR Connected for Zuken RF Verification Flow for PCB Design

AWR Connected for Zuken RF Verification Flow for PCB Design

AWR and Zuken launched AWR Connected for Zuken. The RF verification flow provides a pathway from Zuken’s CR-8000 Design Force PCB design software into AWR’s Microwave Office high-frequency simulation software. AWR Connected for Zuken is available now from AWR. CR-8000 Design Force PCB design suite is available from Zuken.

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Cadence Encounter Digital Platform Optimizes ARM POP IP

ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.

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Synopsys, TowerJazz Announce Qualified Mixed-Signal IC Design Solution for Reference Flow 2.0

Synopsys’ unified mixed-signal IC design solution has been qualified for TowerJazz’s power management analog/mixed-signal reference design flow (Reference Flow 2.0) and 180-nanometer (nm) Power Management (PM) interoperable process design kit (iPDK). Synopsys’ tool suite, the foundry iPDK and reference design flow are verified to seamlessly work together to enable designers to quickly become productive.

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SMIC-Synopsys Reference Flow 5.0 Extends 40nm Low Power Capabilities

SMIC-Synopsys Reference Flow 5.0

Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.

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Cadence Design Systems, Samsung Electronics Team on 20nm Design Methodology

Cadence Design Systems and Samsung Electronics teamed together on a 20-nanometer design methodology. Their 20nm digital design methodology features double patterning technology for joint customer deployment and internal test chips. The new design methodology enables design at 20 nanometers and future process nodes. It is ideal for mobile consumer electronics.

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SMIC 40nm Reference Flow Features Cadence Encounter Digital Technology

Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.

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Cadence Releases New RTL-to-GDSII Flow for Giga-Scale, 20nm Designs

Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting and exceeding the power, performance and area demands of today’s market requirements.

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Cadence, Samsung Foundry Develop DFM Flows for 32nm, 28nm, 20nm Chip Design

Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.

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