'Design Flow' Category Archive

SMIC and Synopsys Reference Flow 4.0

Posted by Ken Cheung in Design Flow, Foundry on Tuesday, June 23, 2009

Synopsys and Semiconductor Manufacturing International Corporation (SMIC) introduced version 4.0 of their 65-nanometer (nm) RTL-to-GDSII reference design flow. The reference flow features support for the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology. The joint solution gives IC engineering teams a proven reference flow to advance SoC designs targeting SMIC’s 65nm process technology [...]

Interconnect and Memory Subsystem Performance Optimization Design Flow

Posted by Ken Cheung in Design Flow on Monday, June 15, 2009

CoWare unveiled the Interconnect and Memory Subsystem Performance Optimization design flow for CoWare Platform Architect. The new design flow enables early and efficient optimization of next-generation system-on-chip (SoC) architectures using ARM AMBA-based virtual platforms. CoWare Platform Architect tool and IP model enhancements and CoWare CoStart services are available immediately for use with the 2009.1.1 release.

Mentor Graphics PADS 9.0 Flow

Posted by Ken Cheung in Design Flow on Tuesday, June 2, 2009

PADS 9.0 flow, from Mentor Graphics, features new levels of functionality, scalability, and integration. PADS design solution helps individuals and design teams to develop PCBs within a highly productive and easy-to-use environment. PADS enables engineers to accomplish a wide breadth and depth of core PCB development tasks — including schematic entry, analog design, signal and [...]

STMicroelectronics ESL SoC Reference Design Flow

Posted by Ken Cheung in Design Flow on Monday, September 15, 2008

STMicroelectronics (NYSE: STM) recently announced a certified electronic system level (ESL) System-on-Chip reference design flow. Aimed at complex designs for next-generation consumer electronics equipment, ST’s integrated ESL reference-design flow for complex digital CMOS designs combines high-level synthesis, sequential equivalence checking, power exploration and lint checkers that look for errors in code construction, thereby providing a [...]

TSMC Reference Flow 9.0

Posted by Ken Cheung in Design Flow on Wednesday, September 10, 2008

Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) recently announced Reference Flow 9.0. The latest version of TSMC’s design methodology lowers design obstacles, improves design margins, and increases yields of its 40nm process technology. Reference Flow 9.0 addresses new design challenges of TSMC’s advanced technologies up to and including 40nm process technology, with features [...]

IMEC Variability Aware Modeling Flow for Sub-45nm

Posted by Ken Cheung in Design Flow on Wednesday, June 11, 2008

IMEC recently announced a variability-aware modeling (VAM) flow that analyzes process variability of sub-45nm technologies which enables designers to optimize their system design for timing, energy and yield versus expected application load. The flow assesses the impact of process variations and degradation effects of sub-45nm technologies on the system performance by giving valuable information to [...]

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