SMIC 40nm Reference Flow Features Cadence Encounter Digital Technology
Semiconductor Manufacturing International Corporation (SMIC) announced a low-power, advanced-node IC design reference flow. The new reference flow features Cadence Encounter digital technology and SMIC’s 40-nanometer manufacturing process. The interoperable, low-power, Common Power Format-based flow helps engineers accelerate and differentiate their low-power, high-performance chips.
Cadence Releases New RTL-to-GDSII Flow for Giga-Scale, 20nm Designs
Cadence Design Systems announced a new RTL-to-GDSII flow. The latest release of the Cadence Encounter RTL-to-GDSII flow features GigaFlex technology, physical-aware synthesis, GigaOpt engine, and differentiated CCOpt technology. The updated flow is ideal for high-performance and giga-scale designs, including those at the latest technology node, 20 nanometers. It enables more efficient development of SoCs, meeting [...]
Cadence, Samsung Foundry Develop DFM Flows for 32nm, 28nm, 20nm Chip Design
Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.
Cadence and GLOBALFOUNDRIES In-Design DRC+ Verification Flow
Cadence Design Systems and GLOBALFOUNDRIES teamed together to reduce the turnaround time for design-for-manufacturing (DFM) signoff at 28 nanometers. Their verification flow features Cadence in-design DFM technology and GLOBALFOUNDRIES DRC+ methodology. The in-design DRC+ verification flow enables engineers to find and fix potential lithography hotspot problems that could reduce yield or even threaten viability of [...]
Synopsys 28nm Design Solutions for TSMC Reference Flow 12.0
Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of [...]
Arteris and EVE Design Flow for System-on-Chip Development
Arteris and EVE teamed together on an integrated solution for system-on-chip (SoC) developers. The design flow enables engineers to generate and use actual SoC register transfer level (RTL) implementations on EVE’s ZeBu-Server emulation platform. The integration flow helps SoC developers create and ship products sooner.
Cadence Digital End-to-end Flow for 28nm Giga-gate/Gigahertz Designs
Cadence Design Systems announced a 28nm digital end-to-end design flow based on Encounter. The digital 28-nanometer flow provides a faster, more deterministic path to achieve giga-gate/gigahertz silicon through technology integration and significant core architecture and algorithm improvements in a unified design, implementation and verification flow. The new Encounter-based flow enables designers to consider the entire [...]
RTL-to-GDSII Silicon Realization Reference Flow for Common Platform
Cadence Design Systems announced a qualified 32/28-nanometer reference flow for the Common Platform technology. The new Silicon Realization reference flow for the Common Platform alliance is built around the Cadence end-to-end Encounter flow, including Encounter RTL Compiler, Encounter Test, Encounter Conformal, the Encounter Digital Implementation System, Litho Physical Analyzer, QRC Extractor, Encounter Timing System, and [...]
Magma Reference Flow for Common Platform 32/28nm Low-Power Process
Magma Design Automation introduced a hierarchical reference flow for the Common Platform alliance’s 32/28-nanometer (nm) low-power process technology. The RTL-to-GDSII reference flow enables designers to reduce power, turnaround time and cost per die. The RTL-to-GDSII reference flow features the Talus IC implementation system’s power optimization and management capabilities, the latest ARM Artisan 32/28-nm LP process [...]
Mentor Graphics and Dongbu HiTek Technology Design Kits for Analog BCDMOS
Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.
If you are familiar with RSS feeds, you can also sign up for our free blog feed. Our RSS feed is updated in real-time while our newsletter is updated daily.
