'Design Flow' Category Archive

Synopsys-SMIC RTL-to-GDSII 90nm Design Flow

Posted by Ken Cheung in Design Flow on Thursday, April 17, 2008

Synopsys, Inc. (NASDAQ: SNPS) and Semiconductor Manufacturing International Corporation (SMIC) (NYSE: SMI)(SEHK: 0981.HK) recently released an enhanced 90 nanometer (nm) hierarchical, multi-voltage RTL-to-GDSII reference design flow that benefits from advanced synthesis, design-for-test (DFT) and design-for-manufacturing (DFM) capabilities. Key features of the reference flow include topographical synthesis in the Design Compiler(tm) Ultra product, scan compression in […]

Low Power Coalition's Common Power Format Roadmap

Posted by Ken Cheung in Design Flow on Wednesday, April 16, 2008

Silicon Integration Initiative (Si2) recently published the Low Power Coalition's (LPC) roadmap for Common Power Format (CPF) extensions planned out through mid-2009. Si2 is an organization of industry-leading semiconductor, systems, EDA, and manufacturing companies focused on improving the way integrated circuits are designed and manufactured in order to speed time to market, reduce costs, and […]

Cadence ARM11, ARM1176JZF-S Reference Methodologies

Posted by Ken Cheung in Design Flow on Monday, January 28, 2008

Cadence Design Systems, Inc. (NASDAQ: CDNS) and ARM [(LSE: ARM); (NASDAQ: ARMHY) created implementation reference methodologies for the ARM11(TM) MPCore(TM) multicore processor and the ARM1176JZF-S(TM) processor. The Cadence reference methodologies for the two ARM processors provide enhanced design solutions for designing multicore, low-power devices.

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