EDA News - 2008.06.05
Synopsys Supports Sun Solaris 10 OS x86_64 Platforms
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced broad support across its advanced electronic design automation (EDA) product lines for Sun Microsystems’ Solaris[TM] 10 Operating System (OS) on x86_64-based systems.
Cypress Hosts Communication Interfaces for Lighting Networks Webinar
Cypress Semiconductor Corp. [...]
EDA News - 2008.06.05 Late Edition
Innovaide Unveils SenseNet Packet Processing, Traffic Management IP
Innovaide Inc. announced the availability of key packet processing and traffic management engines targeting the Carrier Ethernet equipment market. The SenseNet[TM] family of reusable Intellectual Property consists of three hardware blocks - Classification Engine, Forwarding Engine, and Traffic Management Engine.
Altos Variety LX Timing Library Models Qualify on UMC [...]
EDA News - 2008.06.05
Averant Launches New Verification Engine
Averant Inc., a leading provider of advanced verification technology for RTL designs, announces the development of significant new technologies, continuing its First In Formal[tm] leadership in formal property verification.
Berkeley Design Announces Analog FastSPICE Co-Simulation for Verilog
Berkeley Design Automation, Inc. announced the availability of true SPICE accurate analog/RF mixed-signal verification based on [...]
EDA News - 2008.06.04 Late Edition
DreamWorks, Boeing, NASA, WSU Offer Insights to Verifying Complex Systems
Experts from DreamWorks, Boeing, NASA and Washington State University will offer their insights into “Verifying Really Complex Systems: On Earth and Beyond,” during a panel session at the 45th Design Automation Conference (DAC).
Apache Design Solutions DAC Booth Features Methodology Presentations
Apache Design Solutions will host methodology presentations [...]
EDA News - 2008.06.04
GreenSocs Announces DAC Transaction-level Modeling Tutorial
GreenSocs[tm] Ltd announced it will host a technical tutorial during the Design Automation Conference 2008 in Anaheim CA. The tutorial is titled, Writing Efficient TLM 2.0 Models with GreenSocs.
EVE to Break the Billion Cycle Barrier with ZeBu at DAC
Design Automation Conference (DAC) attendees who stop by the EVE booth (#301) [...]
EDA News - 2008.06.03 Late Edition
TSMC Reference Flow 9 Includes GoldTime Statistical Timing Analysis
Extreme DA[tm] announced that TSMC Reference Flow 9.0 covers the GoldTime[tm] Statistical timing analyzer. Supporting 40nm process technology, Reference Flow 9.0 is the latest generation of TSMC’s design methodology to increase yields, lower risks, and reduce design margins.
IMEC, AIXTRON Grow Uniform AlGaN/GaN Heterostructures on 200mm Wafers
IMEC and [...]
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