EDA News – 2008.06.05
Synopsys Supports Sun Solaris 10 OS x86_64 Platforms
Synopsys, Inc. (NASDAQ: SNPS), a world leader in software and IP for semiconductor design and manufacturing, announced broad support across its advanced electronic design automation (EDA) product lines for Sun Microsystems’ Solaris[TM] 10 Operating System (OS) on x86_64-based systems.
Cypress Hosts Communication Interfaces for Lighting Networks Webinar
Cypress Semiconductor Corp. [...]
EDA News – 2008.06.05 Late Edition
Innovaide Unveils SenseNet Packet Processing, Traffic Management IP
Innovaide Inc. announced the availability of key packet processing and traffic management engines targeting the Carrier Ethernet equipment market. The SenseNet[TM] family of reusable Intellectual Property consists of three hardware blocks – Classification Engine, Forwarding Engine, and Traffic Management Engine.
Altos Variety LX Timing Library Models Qualify on UMC [...]
EDA News – 2008.06.05
Averant Launches New Verification Engine
Averant Inc., a leading provider of advanced verification technology for RTL designs, announces the development of significant new technologies, continuing its First In Formal[tm] leadership in formal property verification.
Berkeley Design Announces Analog FastSPICE Co-Simulation for Verilog
Berkeley Design Automation, Inc. announced the availability of true SPICE accurate analog/RF mixed-signal verification based on [...]
EDA News – 2008.06.04 Late Edition
DreamWorks, Boeing, NASA, WSU Offer Insights to Verifying Complex Systems
Experts from DreamWorks, Boeing, NASA and Washington State University will offer their insights into “Verifying Really Complex Systems: On Earth and Beyond,” during a panel session at the 45th Design Automation Conference (DAC).
Apache Design Solutions DAC Booth Features Methodology Presentations
Apache Design Solutions will host methodology presentations [...]
EDA News – 2008.06.04
GreenSocs Announces DAC Transaction-level Modeling Tutorial
GreenSocs[tm] Ltd announced it will host a technical tutorial during the Design Automation Conference 2008 in Anaheim CA. The tutorial is titled, Writing Efficient TLM 2.0 Models with GreenSocs.
EVE to Break the Billion Cycle Barrier with ZeBu at DAC
Design Automation Conference (DAC) attendees who stop by the EVE booth (#301) [...]
EDA News – 2008.06.03 Late Edition
TSMC Reference Flow 9 Includes GoldTime Statistical Timing Analysis
Extreme DA[tm] announced that TSMC Reference Flow 9.0 covers the GoldTime[tm] Statistical timing analyzer. Supporting 40nm process technology, Reference Flow 9.0 is the latest generation of TSMC’s design methodology to increase yields, lower risks, and reduce design margins.
IMEC, AIXTRON Grow Uniform AlGaN/GaN Heterostructures on 200mm Wafers
IMEC and [...]
EDA News – 2008.06.03
Marvell Announces Shiva Embedded CPU Technology
Marvell (NASDAQ: MRVL) raising the bar on performance and low power consumption for embedded CPU applications. Shiva will be integrated in a broad range of Marvell® system-on-a-chip (SoC) products spanning mobile, consumer and enterprise infrastructure applications.
Microchip Announces Application Specific PICtail Plus Daughter Boards
Microchip Technology Inc. announced 10 new and existing [...]
EDA News – 2008.06.02 Late Edition
Semiconductor Chip Sales Grow by 5.9% to $21.2 Billion in April
Worldwide sales of semiconductors of $21.2 billion in April were 5.9 percent higher than the $20.1 billion reported for April 2007, the Semiconductor Industry Association (SIA) reported. April sales were essentially flat sequentially with the $21.2 billion reported for March 2008.
The MathWorks Announces DAC Keynote, [...]
EDA News – 2008.06.02
Logic, TI Announce Zoom Medical OMAP35x Development Kit, SOM
Logic and Texas Instruments Incorporated (TI) (NYSE: TXN) released a new development kit specifically designed to quickly bring new medical products to market. The new Zoom[TM] Medical OMAP35x Development Kit and companion System on Modules (SOMs) use TI’s OMAP35x processor.
Carbon Model Studio Supports STARC Transaction Level Modeling [...]
EDA News – 2008.05.30
Javelin Design Automation Debuts j360 Floorplanning, Prototyping Platform
Javelin Design Automation unveiled its j360[tm] with TrueFit, TruePlan and TruePro specification-driven virtual silicon prototyping platform tool suite for the enterprise customer. Javelin’s j360 can realistically predict and optimize designs for implementation feasibility and quality-of-results (QoR).
Xilinx Announces 3GPP LTE Turbo Encoder and Decoder LogiCORE
Xilinx Inc. (Nasdaq: XLNX) announced [...]
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