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'Models, Simulations' Category Archive

Agilent IC-CAP WaferPro for Device Modeling

Posted by Ken Cheung in Models, Simulations on Thursday, August 19, 2010

Agilent Technologies introduced IC-CAP WaferPro (Integrated Circuit Characterization and Analysis Program Wafer Professional) software. WaferPro is a multi-site, multi-wafer, automated DC and RF measurement solution for semiconductor device modeling applications. IC-CAP WaferPro enables engineers to control semiautomatic and fully automatic probe stations. Agilent WaferPro automates spot and swept measurements across a range of temperatures. WaferPro [...]

White Paper ~ End-To-End System Design: Advantages of an Integrated Tool

Posted by Ken Cheung in Models, Simulations,Research on Thursday, August 12, 2010

AWR Corporation published a new system planning white paper. The AWR white paper outlines the benefits of using a commercial, specialized software program such as Visual System Simulator (VSS) for end-to-end system design, while also embracing legacy approaches with the incorporation of spreadsheet views. The technical paper is available now for AWR.

Silicon Labs Symbol Model Library for Embedded Systems

Posted by Ken Cheung in Microcontrollers,Models, Simulations on Wednesday, August 11, 2010

Silicon Laboratories launched a web-based library of schematic symbols and printed-circuit board (PCB) footprints. The online symbol library features PCB footprints and schematic symbols that are available for download in a vendor neutral format. The library speeds the development of embedded system applications based on Silicon Labs’ embedded mixed-signal products.

Synopsys LTE Model Library Supports Time Division Duplex Mode

Posted by Ken Cheung in Models, Simulations on Wednesday, August 11, 2010

Synopsys has added Time Division Duplex (TDD) mode to their Long-term Evolution (LTE) Model Library for physical layer system simulation. TDD mode helps developers of semiconductors for LTE network equipment and devices to quickly and reliably extend designs to support the third Generation Partnership Project (3GPP) LTE standard. The TDD-enhanced LTE Model Library is available [...]

QUENCH Electromagnetic Software Tool Supports Sumitomo DI-BSSCO

Posted by Ken Cheung in Models, Simulations on Tuesday, August 3, 2010

The QUENCH electromagnetic software tool, from Cobham Technical Services, now features a library containing manufacturer-supplied material characterization data for Sumitomo Electric’s DI-BSSCO bismuth-based superconducting wire. QUENCH is a tool for modeling the quenching process in superconducting materials. The QUENCH tool for modeling the superconducting quenching process is available as part of Cobham’s Opera CAE software [...]

AWR Microwave Office 2010 for Microwave Design

Posted by Ken Cheung in Models, Simulations on Monday, August 2, 2010

AWR introduced 2010 Microwave Office (MWO) design suite for microwave design. The latest release increases productivity for high-frequency monolithic microwave integrated circuit (MMIC), MIC, RF printed circuit board (PCB) and module designers. New features include support for nonlinear behavioral modeling, improved speed in AWR’s multi-rate harmonic balance (MRHB) technology for the design of complex circuits, [...]

AXIEM 3D Planar EM Simulation Software Features Antenna Analysis

Posted by Ken Cheung in Models, Simulations on Monday, June 28, 2010

The 2010 release of AWR AXIEM 3D planar electromagnetic (EM) simulation software now features antenna analysis. AXIEM 2010 includes new features and capabilities that are ideal for large, planar, antenna designs such as arrays with many elements. Critical design problems, such as scan blindness, can now be discovered and corrected. Post-processing such as antenna patterns [...]

Aldec Riviera-PRO 2010.06 RTL and Gate-level Simulator

Posted by Ken Cheung in Models, Simulations on Monday, June 21, 2010

Aldec introduced Riviera-PRO 2010.06 RTL and gate-level simulator. Riviera-PRO 2010.06 supports the Open Verification Methodology (OVM) co-authored by Cadence (NASDAQ:CDNS) and the early release of the Universal Verification Methodology (UVM) from Accellera. OVM and UVM provide common building blocks and predefined mechanisms for building reusable and expandable test environments that take full advantage of SystemVerilog [...]

Extreme DA GoldTime for Altos Variety and Liberate Models

Posted by Ken Cheung in Design Flow,Models, Simulations on Friday, June 11, 2010

Altos Design Automation and Extreme DA developed a signal-integrity (SI) design flow for integrated circuit (IC) designs manufactured at process nodes of 65-nanometers (nm) and below. Extreme DA GoldTime for use with Altos Variety and Liberate models is available now from Extreme DA. Pricing varies depending on configuration. Altos Variety and Liberate approved libraries for [...]

Artisan Studio 7.2 Model Driven Development Tool Suite

Posted by Ken Cheung in Models, Simulations,UML on Thursday, June 3, 2010

Atego introduced the Artisan Studio 7.2 model-driven development tool suite. Artisan Studio has been re-architected to provide role-based Editions which have been specifically designed to make the working environment more relevant and efficient for the specialist needs of Enterprise Architects, Systems Engineers and Software Engineers. Artisan Studio 7.2 features new modeling capabilities and functions.

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