CoFluent Design Combines OMG UML, SysML, and MARTE
CoFluent Design has developed a new methodology that combines the OMG’s (Object Management Group) standards UML (Unified Modeling Language), SysML (System Modeling Language), and MARTE (Modeling and Analysis for Real-Time and Embedded Systems) profile. By offering a link from UML to CoFluent Studio and its automatic SystemC code generation, CoFluent Design makes UML models executable [...]
VeriSilicon ZSP Models for Carbon SoC Designer Virtual Platform
Carbon Design Systems and VeriSilicon have integrated VeriSilicon’s ZSP models into the Carbon SoC Designer virtual platform. VeriSilicon processors enable users to perform implementation-accurate architectural analysis and pre-silicon firmware development. The VeriSilicon ZSP integration is available now from Carbon Design Systems.
Sigrity PowerDC Thermal Simulation and Analysis Software
Sigrity introduced PowerDC Thermal analysis software. PowerDC Thermal eliminates manual iterations between simulations with separate electrical and thermal tools, reduces time, and improves results convergence. It is ideal for avoiding field failures. PowerDC with DC analysis, thermal analysis, and co-simulation capability is available on Windows and Linux platforms. Annual prices start at $30,000. PowerDC Thermal [...]
CoFluent SystemC Library for Questa Functional Verification Platform
CoFluent Studio can now be used for the creation and automatic generation of SystemC models and test cases for the Mentor Graphics Questa functional verification platform. The automatic SystemC transaction-level modeling (TLM) code generation allows reuse of IC and use case models for validating the register-transfer level (RTL) implementation in Questa.
SynaptiCAD 64-Bit Verilog Extreme Simulator
SynaptiCAD launched a 64-bit Linux version of VeriLogger Extreme, which is a Verilog simulation and debug environment. VeriLogger Extreme is available on Linux, Solaris, and MS Windows. A 64-bit Windows version will be released in the near future. A perpetual license sells for $4000 on Windows. Leasing options are also available, as well as a [...]
CoWare-Tensilica Processor Support Package for Multi-Core Designs
CoWare and Tensilica teamed together to further enhance the integration of Tensilica’s processor models into the CoWare tools to support CoWare’s advanced functionality to ease software development on multi-core Tensilica-based SOC (system-on-chip) designs. The enhanced solution is being used by joint CoWare-Tensilica customers in automotive, consumer, and wireless markets. Tensilica Xtensa and Diamond Standard PSPs [...]
EVE Adds Multi-User Capability to ZeBu-Server
ZeBu-Server, from EVE (Emulation & Verification Engineering), now offers superior multi-user capabilities that can support up to 25 users concurrently. Each ZeBu-Server user or design can utilize any of the available resources, and allocation of the emulation resources is completely automatic. Each user can have a dedicated host PC with its own PCIe interface for [...]
Berkeley Design Automation Analog FastSPICE RF
Berkeley Design Automation introduced Analog FastSPICE RF (AFS RF), which is the first true SPICE accurate device noise analysis for RF circuits. AFS RF accurately analyzes nanometer-scale device noise impact for all types of pre-layout and post-layout circuits, ensuring early insight into its impact on performance, power, and area. For complex circuits, Analog FastSPICE RF [...]
Agilent GoldenGate v4.4 for RFIC Simulation, Verification, Analysis
Agilent Technologies rolled out version 4.4 of the GoldenGate software for RFIC simulation, verification and analysis. GoldenGate Release 4.4 features enhanced performance, new key stability and yield analyses, and RF extensions to mixed-signal simulation. GoldenGate version 4.4 improves RFIC design in advanced CMOS technology nodes. The Agilent GoldenGate version 4.4 is available December 2009 and [...]
Pin-level SystemC Models of Xtensa Customizable Dataplane Processors
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing [...]
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