EDA Blog » Microcontrollers

IDC Worldwide PC Microprocessor 3Q10 Stats

Ken Cheung — Thu, 11 Nov 2010 17:28:03 +0000

According to International Data Corporation (IDC), worldwide PC microprocessor unit shipments and revenues in the third calendar quarter of 2010 (3Q10) increased 2.1% and 2.5%, respectively, compared to 2Q10. Worldwide PC microprocessor unit shipments and revenues in the third calendar quarter of 2010 (3Q10) increased 8.6% and 24.1%, respectively, compared to the third quarter of 2009. The findings were published in IDC’s latest PC processor study, Worldwide PC Microprocessor 3Q10 Vendor Shares.

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Silicon Labs Symbol Model Library for Embedded Systems

Ken Cheung — Wed, 11 Aug 2010 18:40:50 +0000

Silicon Laboratories launched a web-based library of schematic symbols and printed-circuit board (PCB) footprints. The online symbol library features PCB footprints and schematic symbols that are available for download in a vendor neutral format. The library speeds the development of embedded system applications based on Silicon Labs’ embedded mixed-signal products.

EEMBC to Benchmark Embedded Processors with Floating Point Units

Ken Cheung — Thu, 01 Apr 2010 17:33:52 +0000

The Embedded Microprocessor Benchmark Consortium (EEMBC) is developing new benchmarks that will track the performance of embedded processors with floating-point hardware units. Floating point (FP) refers to the ability of an embedded processor to crunch numbers that are too large or small to be represented as integers. Many embedded processors include hardware FP units (FPUs) to enable higher levels of precision. The new EEMBC benchmarks will enable embedded system developers to evaluate FPU performance on the basis of consistent and controlled data.

IAR KickStart Kit for NXP LPC1114 Microcontroller

Ken Cheung — Thu, 10 Dec 2009 18:53:46 +0000

IAR Systems introduced the IAR KickStart kit for NXP LPC1114. The IAR KickStart Kit includes a development board fitted with the LPC1114 microcontroller, an 8K KickStart edition of IAR Embedded Workbench for ARM, and a 20-state evaluation edition of IAR visualSTATE. IAR KickStart Kit for LPC1114 is priced at $139 (€ 100). According to IAR Systems, this might be the world’s first commercial starter kit for ARM Cortex-M0-based microcontrollers.

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Viosoft Android Adoption Kit for MIPS Digital Multimedia Designs

Ken Cheung — Wed, 02 Dec 2009 18:18:29 +0000

Viosoft launched the Android Adoption Kit for MIPS-Based digital multimedia designs. The Android Adoption Kit includes Sigma Designs’ Vantage 8654 Development Platform, the Viosoft Arriba IDE/Debugger, access to the latest Android on MIPS and Linux source code from the MIPSAndroid community portal, and online support from Viosoft. The Android Adoption Kit is available now and is priced at $995 (US). For the first 100 customers, Viosoft will discount the full purchase price toward the purchase of the Viosoft Arriba Embedded Linux Edition, or the Android Porting Kit for professional users.

Arriba for Android Porting Kit for the MIPS

Ken Cheung — Thu, 19 Nov 2009 22:17:43 +0000

MIPS Technologies introduced the Arriba for Android Porting Kit (APK) for the MIPS architecture. With the Arriba APK, OEMs can quickly tailor and optimize Android for specific platforms. The Arriba APK is available now. The Arriba APK includes the first year of development tool maintenance, along with 60 days of support from Viosoft. Viosoft’s Arriba tools support single and multi-core platforms, providing support for any MIPS-based Android target. All MIPS processors are supported, from MIPS architecture licensees’ designs to MIPS’ complete offering of licensable cores including the 1004K coherent processing system.

IAR Embedded Workbench Supports TI 4th Gen Stellaris Microcontrollers

Ken Cheung — Tue, 02 Jun 2009 16:00:49 +0000

IAR Embedded Workbench® for ARM® and IAR PowerPac for ARM now supports the fourth generation of Texas Instruments’ ARM Cortex[tm] -M3-based Stellaris® microcontroller (MCU) family. IAR Embedded Workbench for ARM is a set of sophisticated and easy-to-use development tools. It incorporates an ARM Cortex-M3 C/C++ compiler, assembler, linker, librarian, text editor, project manager, and debugger combined in an integrated development environment (IDE) for programming embedded applications.

Evatronix T8051 Microcontroller IP Core

Ken Cheung — Mon, 20 Oct 2008 04:04:28 +0000

Evatronix SA recently introduced the T8051 IP Core, which is the smallest microcontroller that implements Intel 8051 Instruction Set Architecture. The design has one of the best performance-to-size ratios on the market. The T8051 IP core is available for licensing now. Standard deliverables include various sets of scripts for trouble-free synthesis and simulation as well as an extensive Verilog 2001 testbench, while the proprietary prototyping environment can be purchased as an option.

With the CPU’s 2700 gates, the T8051 is ideal for IC designers who want to make use of complete 8-bit architecture functionality while substantially reducing the size of their systems. The lowest possible gate count is especially valuable for engineers working with mixed signal designs implemented in older processes with larger feature sizes, where the silicon area is a significant factor.

The T8051 makes it possible to replace hard-coded control FSM with a programmable microcontroller, which was hard to reach with a significant difference in gate count between the two solutions.

Despite its tiny size, the T8051 is a powerful 8-bit microcontroller. Instruction cycle latency has been tuned to minimize hardware resources, however, the core still performs 4.1 times better than the original Intel 8051 in terms of Dhrystone MIPS per MHz. Communication with both built-in and external memories has been accelerated by de-multiplexing the address and data buses, while alternate port functions such as external interrupts and serial interface are available on separate pins – all this to give the user a possibility to connect and effectively manage a greater number of peripheral devices.

More info: Evatronix

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Microchip MASTERs Conference

Ken Cheung — Mon, 07 Jul 2008 04:02:57 +0000

Microchip Technology Inc. (NASDAQ:MCHP) will hold their Worldwide MASTERs Conference at the JW Marriott Desert Ridge Resort & Spa in Phoenix, Arizona. The main conference will take place from July 23-26 and a pre-conference on July 21 and 22, 2008. The MASTERs Conference offers design engineers a forum for sharing and exchanging technical information on the company’s 8-, 16- and 32-bit PIC microcontrollers, high-performance analog and interface solutions, 16-bit dsPIC digital signal controllers (DSCs), KEELOQ security devices, memory products, and MPLAB development systems — including the industry’s only singular IDE to support an entire 8-, 16- and 32-bit microcontroller portfolio.

The conference is ideal for designers who are looking for solutions to embedded-control challenges or in-depth education on Microchip’s products. Design engineers and engineering managers benefit from the conference by learning about solutions and interfacing with the Microchip architects and developers. Engineers graduating from the MASTERs program are equipped to go out and use Microchip products to their full advantage. The conference courses, a 1G Flash Drive with all class materials, and three-night accommodations with meals and evening entertainment are included in the conference cost of $1,295 USD, with all payments due by July 18th, 2008.

MASTERs is an in-depth, bi-directional exchange of technical information between Microchip experts and the company’s technical partners, including consultants, customers, third parties, distributor FAEs and design houses. Topics presented cover a broad range of subjects, from board layout topologies to real-life reference designs and embedded applications.

MASTERs classes cover the gamut of electronic engineering topics, including hands-on sessions offering instruction for object-oriented programming of PIC microcontrollers and how to do battery authentication, courses on designing LED and LCD display systems, and classes on how to add Ethernet, USB and ZigBee(tm) protocol communication to embedded designs. In addition, there are hands-on workshops that show how to create intelligent power supplies, motor control and how to take full advantage of the dsPIC DSC for speech-processing applications.

Microchip is also offering a two-day pre-conference for those who wish to attend as many classes as possible during the week. These classes are designed for beginner and advanced attendees. For example, “Introduction to Embedded Programming Using C” is a two-day, 16-hour step-by-step crash course in C, with practical hands-on exercises.

More info: MASTERs Conference

10 Years, 10 Lessons: A View from the Multiprocessing Trenches

Ken Cheung — Mon, 16 Jun 2008 11:44:25 +0000

QNX Software Systems is offering a webinar titled, “10 Years, 10 Lessons: A View from the Multiprocessing Trenches.” The one-hour webcast will take place on Tuesday, June 17, 2008, 10 AM PT / 1 PM ET. The online seminar may be of interest to embedded software development managers, architects, and developers who are considering or who are using a multi-core processor for an upcoming project.

Overview

Do you know what you want to achieve with multi-core processing? Are you making the most out of the processor cores in your embedded designs? Whether you have migrated to a multi-core or are still investigating strategies, tune in to this session to hear Kerry Johnson and Robert Craig explore multi-core technology based on their 35 years of combined experience in the industry.

In this web seminar, Kerry Johnson shares the insights gained from QNX Software System’s 10 years of experience in symmetric multiprocessing (SMP) for embedded systems. Kerry argues that adopting a multi-core processor does not have to be an arduous task. The programming approaches are, in fact, well established and within the ability of most embedded software developers today. The real key is to know what you want to accomplish, where to start, and to follow proven, experience-based practices that prevent the “gotchas” and ensure maximum scalability. Join Kerry as he shares 10 lessons learned that will help ensure the success of your next multi-core project.

Robert Craig will then take you through the new QNX developer portal, where there is a description of the key functions used to handle SMP system bring up and inter-processor co-operation, development tools, forums and more to enable migration to multi-core processing.

More information: QNX Software Systems Webinar