Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range of DDR SDRAM standards in a single PHY without sacrificing power consumption or silicon area. The DesignWare DDR multiPHY is available now.
Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock speed, up to 20% smaller die area and up to 15% less power consumption. The Diamond Standard processors are available now.
The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. It is a click-box configuration option with the configurable Xtensa LX3 processor core. Designers can also choose from a number of other configuration options (memories, interfaces, etc.) when designing their core. The ConnX BBE16 and an evaluation kit will be available in the second quarter of 2010.
Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. The enhancements result in up to 40% lower power and up to a 50 percent size reduction.
Synopsys introduced the DesignWare High-Definition Multimedia Interface (HDMI) 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. The DesignWare HDMI IP enables designers to quickly incorporate differentiated functionality into digital TV (DTV) and home theater applications with less risk and improved time-to-market. The DesignWare HDMI 1.4 Tx and Rx IP solution is available now. The HDMI PHY IP is available in more than 10 process technologies from 90-nanometers (nm) to 40-nm, and from leading foundries.
Synopsys introduced three new DesignWare MIPI IP. The DesignWare consists of 3G DigRF Controllers and PHYs for MIPI DigRF V3 standard interface; CSI-2 Synthesizable controller for MIPI CSI-2 Host application; and D-PHY Physical Layer for MIPI CSI-2, DSI, and UniPro standard interfaces. The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller and D-PHY are available now in 65nm and 40nm process technologies.
CEVA launched the Application Optimizer, which is an integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox Software Development Environment, the Application Optimizer enables application developers to easily develop software for CEVA’s DSPs purely in C-Level, eliminating any hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs.
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing RTL simulators. The models also do not require the usage of any specialized hardware/software co-simulation tool.
Synopsys introduced DesignWare data converter IP solutions for 40-nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications, and video designs requiring high-performance, ultra-low power consumption and very compact area. The DesignWare Sigma-Delta ADCs, Current Steering DACs, Video DACs, and General Purpose ADCs and DACs in the 40-nm process are expected to be available in Q1 2010. The DesignWare Data Converter IP solutions are currently available in leading foundries and advanced technology processes from 180-nm to 65-nm.
Synopsys introduced DesignWare USB 2.0 picoPHY IP. The IP supports advanced 28nm processes in a 1.8V architecture, is 30% smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption. The DesignWare USB 2.0 picoPHY is ideal for mobile and high-volume consumer applications such as feature-rich smartphones, mobile internet devices, and netbooks. The DesignWare USB 2.0 picoPHY IP is expected to be available to early adopters starting in Q4 2009 for 28-nm processes, with a roadmap for 40- and 32-nm.