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'IP Cores' Category Archive

Synopsys DesignWare Data Converter IP Solutions for 40nm Process

Posted by Ken Cheung in IP Cores on Tuesday, November 24, 2009

Synopsys introduced DesignWare data converter IP solutions for 40-nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications, and video designs requiring high-performance, ultra-low power consumption and very compact area. The DesignWare Sigma-Delta ADCs, Current Steering DACs, Video DACs, and General Purpose ADCs and DACs in the 40-nm process are expected [...]

Synopsys DesignWare USB 2.0 picoPHY IP

Posted by Ken Cheung in IP Cores on Thursday, October 29, 2009

Synopsys introduced DesignWare USB 2.0 picoPHY IP. The IP supports advanced 28nm processes in a 1.8V architecture, is 30% smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption. The DesignWare USB 2.0 picoPHY is ideal for mobile and high-volume consumer applications such as feature-rich smartphones, mobile [...]

Synopsys DesignWare 96 dB Hi-Fi Audio IP for SMIC 65nm Process

Posted by Ken Cheung in IP Cores on Thursday, October 29, 2009

Synopsys introduced the DesignWare 96 dB Hi-Fi Audio IP in the SMIC 65 nanometer (nm) process. The DesignWare 96 dB Hi-Fi Audio IP for SMIC 65nm processes is expected to be available in Q4 2009. The DesignWare Audio IP solutions are available in leading foundries and advanced technology processes from 180-nm to 65nm. The DesignWare [...]

Open-Silicon, MIPS Technologies, Virage Logic Team on Test Chips

Posted by Ken Cheung in IP Cores on Wednesday, October 28, 2009

Open-Silicon, MIPS Technologies, and Virage Logic teamed to develop test chips showcasing the companies’ technologies for building high-performance processor-based systems. The companies achieved successful 65 nanometer (nm) silicon testing of a processor test chip at 1.1GHz, making it one of the fastest processors built in a 65nm ASIC. In addition, the companies are now working [...]

ARM Cortex-A5 MPCore Processor

Posted by Ken Cheung in IP Cores on Thursday, October 22, 2009

The ARM Cortex-A5 MPCore processor is a small, lowest power ARM multicore processor capable of delivering the Internet. The Cortex-A5 processor is available as an extremely area- and power-efficient uniprocessor or up to a 4x multicore processor. The processor is ideal for ultra low cost handsets, feature phones, smart mobile devices, pervasive embedded devices, consumer [...]

Xtensa 8 Customizable Dataplane Processor Core for Embedded Control

Posted by Ken Cheung in IP Cores on Monday, October 19, 2009

Tensilica announced the Xtensa 8 customizable processor. The Xtensa 8 low-power dataplane processor core (DPU) starts at a size of only 15,000 gates, consuming less than 0.05mm squared in 40nm process technology. It is one of the smallest licensable controller cores on the market. With power dissipation starting at only 12 µW/MHz, it is also [...]

DesignWare DDR3/2 PHY, Controller IP Support 2133 Mbps, 1.35V DDR3L

Posted by Ken Cheung in IP Cores on Wednesday, September 9, 2009

Synopsys DesignWare DDR3/2 PHY and digital controller IP now supports the emerging 1866 and 2133 Megabits per second (Mbps) data rates currently being added to the JEDEC DDR3 standard. The DDR3/2 PHY also supports the Low Voltage DDR3L specification that runs at 1.35V, making the DesignWare IP ideal for power-conscious designs where the change from [...]

apt-X Lossless Audio Compression

Posted by Ken Cheung in IP Cores on Tuesday, September 1, 2009

apt-X Lossless, is APTX’s new, adaptive, lossless audio coding scheme. apt-X Lossless out-performs other lossless audio coding schemes — including FLAC, in a number of emerging application scenarios that depend upon the efficient transmission of high-quality audio over wireless channels and networks. apt-X Lossless audio codec is implemented as C and C++ code, and has [...]

MIPS Technologies and Sigma Designs Enable Android on HD Screens

Posted by Ken Cheung in IP Cores,RTOS,Wireless on Thursday, August 27, 2009

MIPS Technologies and Sigma Designs have teamed together to bring the full high-definition (HD) experience to the Android platform. To enable Android to run on an HD screen rather than the small screen of a mobile handset, Sigma and MIPS enhanced the Android libraries and the MIPS architecture. Sigma Designs extended libraries within Android to [...]

Synopsys DesignWare IP for HDMI Interface

Posted by Ken Cheung in IP Cores on Thursday, August 13, 2009

Synopsys rolled out silicon-proven High-Definition Multimedia Interface (HDMI) transmitter and receiver digital controllers and PHY IP solutions as part of their DesignWare IP portfolio. Synopsys’ DesignWare IP for the HDMI interface is compliant to the standard specification and supports High-bandwidth Digital Content Protection (HDCP). The IP is available in leading process technologies from 90nm down [...]

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