The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of over 1 GHz in 45 nm process technology (45GS) with an area of just 0.044 mm2. The configurable and extensible Xtensa LX4 DPU is available now. The IP core is ideal for handling complex compute-intensive DSP applications where an RTL implementation may be the only other option.
Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.
According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI Express 3.0 is available now.
Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.
Synopsys introduced their new DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP. The Sonic Focus Stereo IPs enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The new Sonic Focus Stereo IP solutions are ideal for low-power DSP and cost-effective embedded stereo audio applications. The Synopsys DesignWare Sonic Focus Stereo IP solutions are available now.
A couple of announcements by Synopsys yesterday: (1) DesignWare ARC AS 221 BD dual-core processor has been optimized for high-definition (HD) audio applications and (2) three new enhancements to their DesignWare ARC 600 32-bit configurable processor family. The DesignWare AS 221 BD and the new enhancement options to the DesignWare ARC 600 family cores are available now. Synopsys’ DesignWare ARC cores enable engineers to lower integration risk and speed time-to-market for their embedded system-on-chip (SoC) designs.
Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not encumbered by patents, and has an open-source reference implementation. Tensilica’s FLAC decoder supports both stereo and multi-channel formats.
Virage Logic has expanded their suite of certified, fully-optimized audio codecs. The codecs are available for the AS 211SFX with dual MAC (Multiplier/Accumulator) and have been fully certified and thoroughly tested. Virage Logic’s Sound-to-Silicon audio solution is a complete hardware and software offering that includes the AS 211SFX, an extensive codec portfolio, the Media Streaming Framework, and the Sonic Focus audio post processing software. The audio codecs are delivered as source code and are developed and supported by Virage Logic.
The Evatronix C65C02 IP core is a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology. The C65C02 is a fast 8-bit microprocessor IP that implements the same instruction set as the 65C02 microprocessor chip, which is an upgraded version of the NMOS-based MOS Technology 6502 8-bit CPU. The Evatronix C65C02 IP core is available for licensing now. The core includes synthesis and simulation support scripts for most environments, Verilog or VHDL test bench, and a reference design for the proprietary evaluation board.
Synopsys introduced the DesignWare Ethernet Quality-of-Service (QoS) Controller IP. Synopsys’ DesignWare Ethernet IP solution supports the IEEE 802.1AS and 802.1-Qav version D6.0 specifications. These specifications enable efficient networking of streaming audio video (AV) applications through IEEE 802.1 networks found in consumer electronics, automotive AV and professional sound system products. The DesignWare Ethernet QoS Controller supporting 10/100/1G data transfer rates is available now.