Virage Logic Expanded Audio Codecs
Virage Logic has expanded their suite of certified, fully-optimized audio codecs. The codecs are available for the AS 211SFX with dual MAC (Multiplier/Accumulator) and have been fully certified and thoroughly tested. Virage Logic’s Sound-to-Silicon audio solution is a complete hardware and software offering that includes the AS 211SFX, an extensive codec portfolio, the Media Streaming [...]
Evatronix 65C02 Microprocessor IP Core
The Evatronix C65C02 IP core is a 65C02 compatible microprocessor IP core that complies with the original 6502 Instruction Set Architecture by MOS Technology. The C65C02 is a fast 8-bit microprocessor IP that implements the same instruction set as the 65C02 microprocessor chip, which is an upgraded version of the NMOS-based MOS Technology 6502 8-bit [...]
Synopsys DesignWare Ethernet Quality-of-Service Controller IP
Synopsys introduced the DesignWare Ethernet Quality-of-Service (QoS) Controller IP. Synopsys’ DesignWare Ethernet IP solution supports the IEEE 802.1AS and 802.1-Qav version D6.0 specifications. These specifications enable efficient networking of streaming audio video (AV) applications through IEEE 802.1 networks found in consumer electronics, automotive AV and professional sound system products. The DesignWare Ethernet QoS Controller supporting [...]
Tensilica ConnX 545CK 8-MAC VLIW Digital Signal Processor Core
Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die [...]
Synopsys DesignWare DDR multiPHY IP Solutions
Synopsys introduced the DesignWare DDR multiPHY. The IP solutions are mixed-signal PHY IP Cores that supply the complete physical interface to JEDEC standard DDR3, DDR3L (1.35V DDR3), DDR3U (1.2xV DDR3), DDR2, Mobile DDR and LPDDR2 SDRAM Memories up to 1066Mbps data rates. Synopsys DesignWare DDR multiPHY IP solutions are designed to support a broad range [...]
Tensilica Third Generation Diamond Standard Controllers
Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock [...]
Tensilica ConnX BBE16 BaseBand Engine DSP
The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. [...]
Tensilica HiFi EP Audio DSP IP Core
Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. [...]
Synopsys DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions
Synopsys introduced the DesignWare High-Definition Multimedia Interface (HDMI) 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. The DesignWare HDMI IP enables designers to quickly incorporate differentiated functionality into digital TV (DTV) and home theater applications with less risk and improved time-to-market. The DesignWare HDMI [...]
Synopsys DesignWare 3G DigRF, CSI-2 Controller, and D-PHY MIPI IP
Synopsys introduced three new DesignWare MIPI IP. The DesignWare consists of 3G DigRF Controllers and PHYs for MIPI DigRF V3 standard interface; CSI-2 Synthesizable controller for MIPI CSI-2 Host application; and D-PHY Physical Layer for MIPI CSI-2, DSI, and UniPro standard interfaces. The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller [...]
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