Category Archives: IP Cores

ip, core

Tensilica Debuts HiFi Mini Digital Signal Processor IP Core

Tensilica announced their HiFi Mini DSP IP core. According to the company, the digital signal processor core is the smallest, lowest power DSP IP core supporting always listening voice trigger and speech command modes. The HiFi Mini DSP IP core will be available in March 2013. The core is ideal for smartphones, tablets, appliances, and automotive applications.

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Cadence Encounter Digital Platform Optimizes ARM POP IP

ARM and Cadence Design Systems teamed together to create a solution that uses the Cadence Encounter digital platform to optimize ARM POP intellectual property (IP) technology for the Cortex-A9 processor on the TSMC 40LP process, including ultra low threshold voltage (uLVT). The combined solution is available for license from ARM to accelerate the implementation of ARM processors.

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Synopsys DesignWare IP Available for SMIC 40-nanometer Low-Leakage Process

Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.

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Cortus Introduces APS5 Embedded Microcontroller IP Core

Cortus APS5 microcontroller IP core

Cortus announced their APS5 embedded microcontroller. The Cortus APS5 is a 32-bit general purpose CPU. The processor IP is designed for demanding embedded systems. It features a high performance integer unit and an instruction cache. The APS5 can be implemented in dual- or quad-core configurations or be used in a heterogeneous system with APS3R.

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Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core

Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.

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Cadence Introduces 40/100 GbE MAC and PCS IP Cores

Cadence Design Systems introduced 40/100 Gigabit Ethernet media access controller and physical coding sub-layer IP cores. The new Cadence 40/100 GbE MAC and PCS IP cores speed the deployment of SoCs for networking and high-performance computing. The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available now.

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Synopsys Debuts DesignWare HDMI 1.4 PHY IP in 28nm Processes for Multiple Foundries

Synopsys introduced version 1.4 of their DesignWare HDMI (High-Definition Multimedia Interface). The PHY IP is available in advanced 28 nanometer processes for multiple foundries. Availability of DesignWare HDMI 1.4 IP on multiple 28nm processes ensures designers have access to the high-quality, silicon-proven IP so they they can quickly incorporate the latest audio and video functionality into next-generation mobile and digital home devices. DesignWare HDMI 1.4 PHY IP is available now in 90nm to 28nm process nodes. The DesignWare HDMI 1.4 TX and RX digital controllers are also available now.

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Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core

Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement of over 150% for most voice codecs compared to HiFi EP. The HiFi 3 has been delivered to lead customers. General availability will be in March.

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Cadence Memory Controller and PHY IP Supports ONFI 3

Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. The Cadence ONFI 3 memory controller and PHY IP are available now. The EDA company is also offering supporting verification IP (VIP) and memory models to ensure successful implementation.

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Synopsys DesignWare AEON NVM IP Available for 180nm Process

Synopsys announced DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP includes few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. DesignWare AEON embedded NVM IP is also available for 65nm to 250nm process technologies. DesignWare AEON NVM IP is ideal for wireless, RFID and analog and mixed-signal SoC designs.

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