EDA Blog » IP Cores

Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core

Ken Cheung — Wed, 29 Feb 2012 18:16:24 +0000

Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.

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Cadence Introduces 40/100 GbE MAC and PCS IP Cores

Ken Cheung — Tue, 21 Feb 2012 17:14:23 +0000

Cadence Design Systems introduced 40/100 Gigabit Ethernet media access controller and physical coding sub-layer IP cores. The new Cadence 40/100 GbE MAC and PCS IP cores speed the deployment of SoCs for networking and high-performance computing. The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available now.

Synopsys Debuts DesignWare HDMI 1.4 PHY IP in 28nm Processes for Multiple Foundries

Ken Cheung — Tue, 14 Feb 2012 16:23:58 +0000

Synopsys introduced version 1.4 of their DesignWare HDMI (High-Definition Multimedia Interface). The PHY IP is available in advanced 28 nanometer processes for multiple foundries. Availability of DesignWare HDMI 1.4 IP on multiple 28nm processes ensures designers have access to the high-quality, silicon-proven IP so they they can quickly incorporate the latest audio and video functionality into next-generation mobile and digital home devices. DesignWare HDMI 1.4 PHY IP is available now in 90nm to 28nm process nodes. The DesignWare HDMI 1.4 TX and RX digital controllers are also available now.

Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core

Ken Cheung — Tue, 10 Jan 2012 17:51:04 +0000

Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement of over 150% for most voice codecs compared to HiFi EP. The HiFi 3 has been delivered to lead customers. General availability will be in March.

Cadence Memory Controller and PHY IP Supports ONFI 3

Ken Cheung — Mon, 09 Jan 2012 18:14:45 +0000

Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. The Cadence ONFI 3 memory controller and PHY IP are available now. The EDA company is also offering supporting verification IP (VIP) and memory models to ensure successful implementation.

Synopsys DesignWare AEON NVM IP Available for 180nm Process

Ken Cheung — Mon, 27 Jun 2011 16:10:01 +0000

Synopsys announced DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP includes few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. DesignWare AEON embedded NVM IP is also available for 65nm to 250nm process technologies. DesignWare AEON NVM IP is ideal for wireless, RFID and analog and mixed-signal SoC designs.

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Tensilica Xtensa LX4 Dataplane Processing Unit IP Core

Ken Cheung — Wed, 30 Mar 2011 14:27:51 +0000

The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of over 1 GHz in 45 nm process technology (45GS) with an area of just 0.044 mm². The configurable and extensible Xtensa LX4 DPU is available now. The IP core is ideal for handling complex compute-intensive DSP applications where an RTL implementation may be the only other option.

Cadence Wide I/O Memory Controller IP Core

Ken Cheung — Mon, 28 Mar 2011 20:27:00 +0000

Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.

Synopsys DesignWare IP for PCI Express 3.0

Ken Cheung — Tue, 01 Mar 2011 15:39:45 +0000

According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI Express 3.0 is available now.

Synopsys Enhanced DesignWare Universal DDR Memory Controller

Ken Cheung — Thu, 10 Feb 2011 15:46:51 +0000

Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.