EDA Blog » IP Cores

Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core

Ken Cheung — Tue, 10 Jan 2012 17:51:04 +0000

Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement of over 150% for most voice codecs compared to HiFi EP. The HiFi 3 has been delivered to lead customers. General availability will be in March.

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Cadence Memory Controller and PHY IP Supports ONFI 3

Ken Cheung — Mon, 09 Jan 2012 18:14:45 +0000

Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation for maximum performance. The Cadence ONFI 3 memory controller and PHY IP are available now. The EDA company is also offering supporting verification IP (VIP) and memory models to ensure successful implementation.

Synopsys DesignWare AEON NVM IP Available for 180nm Process

Ken Cheung — Mon, 27 Jun 2011 16:10:01 +0000

Synopsys announced DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP includes few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. DesignWare AEON embedded NVM IP is also available for 65nm to 250nm process technologies. DesignWare AEON NVM IP is ideal for wireless, RFID and analog and mixed-signal SoC designs.

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Tensilica Xtensa LX4 Dataplane Processing Unit IP Core

Ken Cheung — Wed, 30 Mar 2011 14:27:51 +0000

The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of over 1 GHz in 45 nm process technology (45GS) with an area of just 0.044 mm². The configurable and extensible Xtensa LX4 DPU is available now. The IP core is ideal for handling complex compute-intensive DSP applications where an RTL implementation may be the only other option.

Cadence Wide I/O Memory Controller IP Core

Ken Cheung — Mon, 28 Mar 2011 20:27:00 +0000

Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by a high-profile customer on two separate projects.

Synopsys DesignWare IP for PCI Express 3.0

Ken Cheung — Tue, 01 Mar 2011 15:39:45 +0000

According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI Express 3.0 is available now.

Synopsys Enhanced DesignWare Universal DDR Memory Controller

Ken Cheung — Thu, 10 Feb 2011 15:46:51 +0000

Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare Universal DDR Memory Controller single-port configuration will be available next month.

Synopsys DesignWare Sonic Focus Stereo and Stereo HD IP

Ken Cheung — Thu, 06 Jan 2011 16:52:55 +0000

Synopsys introduced their new DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP. The Sonic Focus Stereo IPs enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The new Sonic Focus Stereo IP solutions are ideal for low-power DSP and cost-effective embedded stereo audio applications. The Synopsys DesignWare Sonic Focus Stereo IP solutions are available now.

Synopsys DesignWare ARC AS 221 Processor Core for Bluray Disc Players

Ken Cheung — Fri, 19 Nov 2010 15:40:51 +0000

A couple of announcements by Synopsys yesterday: (1) DesignWare ARC AS 221 BD dual-core processor has been optimized for high-definition (HD) audio applications and (2) three new enhancements to their DesignWare ARC 600 32-bit configurable processor family. The DesignWare AS 221 BD and the new enhancement options to the DesignWare ARC 600 family cores are available now. Synopsys’ DesignWare ARC cores enable engineers to lower integration risk and speed time-to-market for their embedded system-on-chip (SoC) designs.

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Tensilica FLAC Decoder for the Xtensa HiFi Audio DSP

Ken Cheung — Wed, 30 Jun 2010 17:28:37 +0000

Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not encumbered by patents, and has an open-source reference implementation. Tensilica’s FLAC decoder supports both stereo and multi-channel formats.