Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core
Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW [...]
Cadence Introduces 40/100 GbE MAC and PCS IP Cores
Cadence Design Systems introduced 40/100 Gigabit Ethernet media access controller and physical coding sub-layer IP cores. The new Cadence 40/100 GbE MAC and PCS IP cores speed the deployment of SoCs for networking and high-performance computing. The design IP, including MAC and PCS, as well VIP, emulation and virtual prototyping support, are available now.
Synopsys Debuts DesignWare HDMI 1.4 PHY IP in 28nm Processes for Multiple Foundries
Synopsys introduced version 1.4 of their DesignWare HDMI (High-Definition Multimedia Interface). The PHY IP is available in advanced 28 nanometer processes for multiple foundries. Availability of DesignWare HDMI 1.4 IP on multiple 28nm processes ensures designers have access to the high-quality, silicon-proven IP so they they can quickly incorporate the latest audio and video functionality [...]
Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core
Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement [...]
Cadence Memory Controller and PHY IP Supports ONFI 3
Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation [...]
Synopsys DesignWare AEON NVM IP Available for 180nm Process
Synopsys announced DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP includes few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. DesignWare AEON embedded NVM IP is also available for 65nm to 250nm process technologies. DesignWare AEON NVM IP [...]
Tensilica Xtensa LX4 Dataplane Processing Unit IP Core
The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of [...]
Cadence Wide I/O Memory Controller IP Core
Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by [...]
Synopsys DesignWare IP for PCI Express 3.0
According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI [...]
Synopsys Enhanced DesignWare Universal DDR Memory Controller
Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare [...]
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