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'IP Cores' Category Archive

Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core

Posted by Ken Cheung in DSPs,IP Cores on Tuesday, January 10, 2012

Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement [...]

Cadence Memory Controller and PHY IP Supports ONFI 3

Posted by Ken Cheung in IP Cores on Monday, January 9, 2012

Cadence Design Systems expanded its Flash IP offering to include support for the Open NAND Flash Interface (ONFI) 3.0 specification. According to Cadence, it is the first company to provide a combined ONFI 3 controller and PHY IP solution. The enhanced Flash IP streamlines SoC and system design while ensuring an optimized ONFI 3 implementation [...]

Synopsys DesignWare AEON NVM IP Available for 180nm Process

Posted by Ken Cheung in IP Cores on Monday, June 27, 2011

Synopsys announced DesignWare AEON Non-Volatile Memory (NVM) IP for multiple 180-nanometer (nm) process technologies. The DesignWare AEON NVM IP includes few-time programmable (FTP), multiple-time programmable (MTP) radio-frequency identification (RFID) and erasable programmable read-only memory (EEPROM) IP solutions. DesignWare AEON embedded NVM IP is also available for 65nm to 250nm process technologies. DesignWare AEON NVM IP [...]

Tensilica Xtensa LX4 Dataplane Processing Unit IP Core

Posted by Ken Cheung in IP Cores on Wednesday, March 30, 2011

The Xtensa LX4 DPU (dataplane processing unit), from Tensilica, features local data memory bandwidth of up to 1024 bits per cycle, wider VLIW (very long instruction word) instructions up to 128 bits for increased parallel processing, and a cache memory prefetch option for reducing cycle counts. The base Xtensa LX4 DPU can reach speeds of [...]

Cadence Wide I/O Memory Controller IP Core

Posted by Ken Cheung in IP Cores on Monday, March 28, 2011

Cadence Design Systems introduced a licensable, wide I/O memory controller core for mobile applications like smartphones and tablets. The new Cadence IP core delivers up to four times the performance of conventional memory interfaces. The wide I/O memory controller and supporting VIP are available now. According to Cadence, the IP is already in use by [...]

Synopsys DesignWare IP for PCI Express 3.0

Posted by Ken Cheung in IP Cores on Tuesday, March 1, 2011

According to Synopsys, it is the first IP provider to support the final version of the PCI Express (PCIe) 3.0 base specification (version 1.0). DesignWare digital controllers for PCI Express now also support the latest PIPE 3.0 specification (v0.9), PCI-SIG Engineering Change Notifications (ECNs), 256-bit datapath and embedded DMA engine. Synopsys’ DesignWare IP for PCI [...]

Synopsys Enhanced DesignWare Universal DDR Memory Controller

Posted by Ken Cheung in IP Cores on Thursday, February 10, 2011

Synopsys enhanced their DesignWare Universal DDR Memory Controller (uMCTL2). The enhanced version offers up to 30% lower latency and up to 15% higher throughput than the previous generation controller. The enhanced uMCTL combines the previous-generation DesignWare Universal DDR memory controller with the the Intelli architecture acquired from Virage Logic. The enhanced version of the DesignWare [...]

Synopsys DesignWare Sonic Focus Stereo and Stereo HD IP

Posted by Ken Cheung in IP Cores on Thursday, January 6, 2011

Synopsys introduced their new DesignWare Sonic Focus Stereo and Stereo HD (High-Definition) IP. The Sonic Focus Stereo IPs enable system-on-chip (SoC) designers and original equipment manufacturers (OEMs) to enhance audio quality and deliver an immersive audio experience for a broad range of low power, DSP-based consumer electronics devices. The new Sonic Focus Stereo IP solutions [...]

Synopsys DesignWare ARC AS 221 Processor Core for Bluray Disc Players

Posted by Ken Cheung in IP Cores on Friday, November 19, 2010

A couple of announcements by Synopsys yesterday: (1) DesignWare ARC AS 221 BD dual-core processor has been optimized for high-definition (HD) audio applications and (2) three new enhancements to their DesignWare ARC 600 32-bit configurable processor family. The DesignWare AS 221 BD and the new enhancement options to the DesignWare ARC 600 family cores are [...]

Tensilica FLAC Decoder for the Xtensa HiFi Audio DSP

Posted by Ken Cheung in DSPs,IP Cores on Wednesday, June 30, 2010

Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not [...]

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