Tensilica Third Generation Diamond Standard Controllers
Tensilica launched the third generation of their Diamond Standard controllers. The Diamond Standard processor cores is based on a common Xtensa architecture and provides the price/performance/low-power required for a wide range of embedded control functions in today’s compute-intensive dataplane functions. Improvements in this third generation of Diamond Standard controllers deliver up to 15% faster clock [...]
Tensilica ConnX BBE16 BaseBand Engine DSP
The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. [...]
Tensilica HiFi EP Audio DSP IP Core
Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. [...]
Synopsys DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions
Synopsys introduced the DesignWare High-Definition Multimedia Interface (HDMI) 1.4 transmitter (Tx) and receiver (Rx) digital controllers and PHY IP solutions that are compliant to the standard specification. The DesignWare HDMI IP enables designers to quickly incorporate differentiated functionality into digital TV (DTV) and home theater applications with less risk and improved time-to-market. The DesignWare HDMI [...]
Synopsys DesignWare 3G DigRF, CSI-2 Controller, and D-PHY MIPI IP
Synopsys introduced three new DesignWare MIPI IP. The DesignWare consists of 3G DigRF Controllers and PHYs for MIPI DigRF V3 standard interface; CSI-2 Synthesizable controller for MIPI CSI-2 Host application; and D-PHY Physical Layer for MIPI CSI-2, DSI, and UniPro standard interfaces. The DesignWare 3G DigRF master and slave controllers and PHY, CSI-2 host controller [...]
CEVA Application Optimizer for C-based Development of DSP Cores
CEVA launched the Application Optimizer, which is an integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox Software Development Environment, the Application Optimizer enables application developers to easily develop software for CEVA’s DSPs purely in C-Level, eliminating any hand-written assembly coding. This results [...]
Pin-level SystemC Models of Xtensa Customizable Dataplane Processors
Tensilica introduced pin-level SystemC models of the Xtensa customizable dataplane processors (DPUs). The pin-level models are a natural extension of Tensilica’s pre-existing transaction-level (TLM) Xtensa SystemC models (XTSC). They enable designers to conduct deep simulations of the interaction between the DPUs and special-function RTL (register-transfer-level) hardware blocks at a cycle-by-cycle pin-accurate level within their existing [...]
Synopsys DesignWare Data Converter IP Solutions for 40nm Process
Synopsys introduced DesignWare data converter IP solutions for 40-nanometer (nm) process technologies. The IP is targeted at broadband wireless communications, wired communications, and video designs requiring high-performance, ultra-low power consumption and very compact area. The DesignWare Sigma-Delta ADCs, Current Steering DACs, Video DACs, and General Purpose ADCs and DACs in the 40-nm process are expected [...]
Synopsys DesignWare USB 2.0 picoPHY IP
Synopsys introduced DesignWare USB 2.0 picoPHY IP. The IP supports advanced 28nm processes in a 1.8V architecture, is 30% smaller than the previous USB 2.0 PHY generation, and offers reduced pin count and low standby power consumption. The DesignWare USB 2.0 picoPHY is ideal for mobile and high-volume consumer applications such as feature-rich smartphones, mobile [...]
Synopsys DesignWare 96 dB Hi-Fi Audio IP for SMIC 65nm Process
Synopsys introduced the DesignWare 96 dB Hi-Fi Audio IP in the SMIC 65 nanometer (nm) process. The DesignWare 96 dB Hi-Fi Audio IP for SMIC 65nm processes is expected to be available in Q4 2009. The DesignWare Audio IP solutions are available in leading foundries and advanced technology processes from 180-nm to 65nm. The DesignWare [...]
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