'IP Cores' Category Archive

The SPIRIT Consortium Merges with Accellera

Posted by Ken Cheung in IP Cores on Friday, June 12, 2009

The organizations’ Boards of Accellera and The SPIRIT Consortium have agreed to a merger of the two Electronic Design Automation (EDA) industry organizations. The union improves the development of language-based and IP standards. Accellera is the leading standards organization developing language-based standards used by system, semiconductor, Intellectual Property (IP) and EDA companies. The SPIRIT Consortium [...]

Synopsys DesignWare SATA IP for SATA 6Gbps Data Transfer Rate

Posted by Ken Cheung in IP Cores on Wednesday, May 27, 2009

Synopsys unveiled the DesignWare SATA AHCI host and device digital controller IP for the latest SATA 6 Gigabit per second (Gbps) data transfer rate as defined in the Serial ATA (SATA) Revision 3.0 specification. This doubles the data rate of the previous (version 2.6) specification. DesignWare SATA IP speeds the deployment of the 6Gbps interface [...]

SystemRDL 1.0 Specification for IP Blocks

Posted by Ken Cheung in IP Cores, Models, Simulations on Monday, May 18, 2009

The SPIRIT Consortium released the SystemRDL specification. SystemRDL is a language for the design and delivery of registers to be used in IP blocks within electronic designs. The SystemRDL semantics support the entire life-cycle of registers from specification, model generation, and design verification to maintenance and documentation. Registers are not just limited to traditional configuration [...]

SMIC 65-nanometer Low Leakage Process IP Portfolio

Posted by Ken Cheung in Foundry, IP Cores on Friday, May 15, 2009

Semiconductor Manufacturing International Corporation (SMIC) announced a set of 65-nanometer low leakage process IPs. SMIC’s new 65nm IPs includes a set of six memory compilers, which enable the intelligent and rapid generation of memory blocks in bulk and on the fly. The compilers feature memories optimized for very high performance and also optimized for performance [...]

MIPS Technologies Sells Analog Business Group to Synopsys

Posted by Ken Cheung in IP Cores on Friday, May 8, 2009

Synopsys has acquired the Analog Business Group of MIPS Technologies for $22 million in cash. As a result of the acquisition, Synopsys’ DesignWare intellectual property (IP) portfolio will gain a new family of analog IP such as Analog-to-Digital Converters, Digital-to-Analog Converters, Audio Codecs, and Power Management. It will also add HDMI TX and RX protocols [...]

OCP 3.0 Specification Ready for Review

Posted by Ken Cheung in IP Cores on Wednesday, May 6, 2009

Open Core Protocol International Partnership (OCP-IP) released the OCP 3.0 specification for member review. The thrid version supports cache coherence, more aggressive power management, an additional high-speed consensus profile, and other new elements. Work on OCP 3.0 was conducted by members of the OCP-IP Specification Working Group including: MIPS Technologies, Nokia, Sonics Inc, Texas Instruments, [...]

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