FTDI Chip has released its second Application Oriented Controller (AOC), the FT51, claimed to be one of the highest performance 8051-compatible cores available. This AOC uses a highly effective processor core, a number of ADCs and DACs, and a variety of interconnects.
The hardware-accelerated Constant False Alarm Rate (CFAR) IP from EnSilica is designed for use in situational awareness radar sensors for car driver-assist apps. It allows the application processor to be freed up by providing a marked-up radar image.
Synopsys introduced their new DesignWare ARC EM SEP (Safety Enhancement Package) Processor core for automotive safety-compliant applications. The ARC EM SEP core is configurable to meet the performance, power and area requirements of each target application. Giving designers the ability to define custom instructions facilitates the integration of proprietary hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required — critical requirements in embedded automotive designs.
Cadence Design Systems announced a suite of ultra-fast, low-power analog intellectual property (IP) products. The new data converter family includes 7-bit 3GSPS dual ADC and DAC, 11-bit 1.5GSPS dual ADC, and 12-bit 2GSPS dual DAC. The converters are ideal for designers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60 GHz spectrum with potential data throughput up to 7Gbps, as well as LTE and LTE Advanced. The Cadence 28nm Data Convertor IP family is available now.
Cadence Design Systems introduced the Secure Digital (SD) 4.0 Host Controller Intellectual Property core. The IP core helps designers achieve the maximum memory card access performance of up to 312MB/s (three times the performance of the previous specification). The Secure Digital 4.0 Host Controller IP core is available now.
Synopsys introduced their DesignWare HDMI 2.0 TX/RX IP solutions. The DesignWare HDMI 2.0 IP solution includes controller, PHY, and example Linux drivers. The solution reduce designers’ integration risk and time-to-market. The DesignWare HDMI 2.0 RX/TX Controller and PHY IP are available now in 28-nm process nodes from multiple foundries.
Synopsys introduced optimized Dolby MS11 Multistream Decoder for the DesignWare ARC AS211SFX and AS221BD audio processors. The MS11 Multistream Decoder is a single-package technology solution for decoding Dolby Digital Plus, Dolby Digital, and Dolby Pulse (AAC LC, HE AAC, and HE AAC v.2) audio formats. The Synopsys Dolby MS11 decoder, optimized for the AS211SFX and AS221BD audio processors, is available now.
Synopsys introduced their DesignWare Sensor IP Subsystem, which is a complete and integrated hardware and software solution for sensor control applications. The DesignWare Sensor IP Subsystem reduces integration effort and cost. The Synopsys DesignWare Sensor IP Subsystem is expected to be available in October of this year to early adopters. General availability is planned for the fourth quarter of 2013.
The Synopsys DesignWare Data Converter IP is available now in the 28-nanometer process node. The data converter IP portfolio includes DesignWare analog-to-digital converters (ADCs), digital-to-analog converters (DACs) and integrated PLLs. The broad DesignWare IP portfolio includes complete interface IP solutions consisting of controllers, PHY and verification IP for widely used protocols, analog IP, embedded memories, logic libraries, processor cores and subsystems.
Tensilica announced their imaging and video dataplane processor. The IVP DSP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing. The IP core supports increasing sensor resolutions. The IVP DPU is available for broad licensing now. The core is ideal for the complex image/video signal processing functions in mobile handsets, tablets, digital televisions (DTV), automotive, video games and computer vision based applications.