Avnet Memec Actel Ultra Low Power Workshops
Avnet Memec recently announced their Actel Ultra-Low Power SpeedWay Design Workshop. The “how to” workshops provide hands-on experience to designers interested in leveraging Actel’s 5-microwatt IGLOO field-programmable gate arrays (FPGAs) for battery-operated and portable applications. Developed by Avnet’s factory-certified field application engineers (FAEs), the $49 Actel Ultra-Low Power workshops will be available through August 26, [...]
Across the Network – 2007.12.21
Renesas RX Family of Microcontrollers
Renesas Technology recently announced a new CISC (Complex Instruction Set Computer) CPU architecture. The new architecture will improve code efficiency, processing performance, and power consumption. CISC microcontrollers (MCUs) based on the new architecture will be branded as the ‘RX’ family (RX stands for Renesas eXtreme). The new RX architecture will unifying [...]
Across the Network – 2007.12.14
Altera Zero-Power MAX IIZ CPLDs
Altera Corporation (NASDAQ: ALTR) created the zero-power MAX® IIZ CPLD to address the power, package and price constraints of the portable applications market. Offering a resource advantage of up to six times the density and three times the I/Os compared to competing traditional macrocell-based CPLDs, MAX IIZ devices allow designers to [...]
Across the Network – 2007.12.07
Summit SMB137 Programmable Battery Charger IC
Summit Microelectronics’ SMB137 programmable battery charger IC was designed for mobile consumer electronics. Dual (USB or AC/DC) inputs and outputs (System or Battery) with CurrentPath(TM) automatic arbitration allow system operation with any input source, any battery charge state, or even missing battery. Proprietary TurboCharge(TM) technology yields dramatic reductions in charge [...]
Tips for FPGA Timing Closure
Lattice is offering a webcast for FPGA designers. The one-hour event will take place Wednesday, March 28, 2007 at 11:00 am Pacific time (2:00 pm Eastern). Here’s the webinar blurb:
Overview
FPGA designers often find themselves squeezing every last bit of performance out of the least expensive, slowest speed grade, device available. In this presentation, Lattice Semiconductor [...]
Altera FPGAs Drive SDR at Software Radio Summit
At the Software Radio Summit, Altera will be featuring:
SDR waveform design flow for Software Communication Architecture (SCA), Common Object Request Broker Architecture (CORBA) and Serial RapidIO(TM) applications
Demos of WiMAX waveforms used by military systems developers
Altera’s SDR experts will discuss:
Addressing size, weight and power (SWaP) requirements with Altera’s new 65-nm Stratix(R) III FPGA family
Using Programmable Power [...]
Altera Stratix III FPGA Web Seminars
Altera has a two web seminars about its new 65-nm high-end Stratix(R) III FPGA family:
Overview of Altera’s 65-nm Stratix III FPGAs
This 15-min QuickCast discusses how Altera’s Stratix III 65-nm high-end FPGAs meet your business and technical requirements. In this QuickCast, you’ll learn more about:
Altera’s methodology for delivering programmable logic solutions to meet the next-generation business [...]
Embedded Design with LatticeMico32 Open, Free 32-bit Soft Processor
Lattice will be giving away an ispLEVER Development Tool for Lattice FPGA and CPLD design to one participant of their upcoming web seminar, Embedded Design with LatticeMico32 Open, Free 32-bit Soft Processor.
The one-hour webcast will take place on Wednesday, October 18, 2006 at 11:00 am Pacific time (2:00 pm Eastern). In the online seminar, you [...]
Actel’s Flash FPGAs Defeat Attacks by Earth
According to a comprehensive third-party investigation, Actel’s flash-based field-programmable gate arrays (FPGAs) are immune to configuration upsets caused by high-energy neutrons naturally generated in the earth’s atmosphere. The study also determined that advances in semiconductor manufacturing technology have had a detrimental impact on the reliability of SRAM-based FPGAs, making them more vulnerable to neutron-induced configuration [...]
EE Times FPGA Users Survey
According to the EE Times 2006 EDA Users Survey, FPGA complexity and speed are rapidly increasing, and as a result, FPGA designers are confronting many of the same issues — and adopting some of the same tools — as their counterparts in ASIC and IC design. Here are some excerpts:
Engineers are expecting average gate counts [...]
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