Category Archives: FPGAs

field programmable gate arrays, pld, configurable processors, fpga, structured ASICs

Avnet Memec Actel Ultra Low Power Workshops

Avnet Memec recently announced their Actel Ultra-Low Power SpeedWay Design Workshop. The “how to” workshops provide hands-on experience to designers interested in leveraging Actel’s 5-microwatt IGLOO field-programmable gate arrays (FPGAs) for battery-operated and portable applications. Developed by Avnet’s factory-certified field application engineers (FAEs), the $49 Actel Ultra-Low Power workshops will be available through August 26, 2008, in 36 locations throughout North America.All participants will receive Actel’s battery-powered IGLOO Icicle Kit and a 7-segment digital multi-meter – a $100 value.

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Across the Network – 2007.12.21

Renesas RX Family of Microcontrollers
Renesas Technology recently announced a new CISC (Complex Instruction Set Computer) CPU architecture. The new architecture will improve code efficiency, processing performance, and power consumption. CISC microcontrollers (MCUs) based on the new architecture will be branded as the ‘RX’ family (RX stands for Renesas eXtreme). The new RX architecture will unifying Renesas’ existing CISC architectures into a single platform. The new platform will be compatible with existing CISC products. The first of the enhanced MCUs are expected to become available in the second quarter of 2009. The primary target markets include office automation, digital consumer electronics, industrial systems, and other embedded applications.

AKA LCD Controller IP
Advanced Knowledge Associates (AKA) announced that LCD driver core IP is now available as standard on its range of Prepackaged Reconfigurable Integrated System-on-Module (PRISM) solutions. This removes the need for any external controller or device because video displays can be driven directly from the PRISM’s FPGA. It also simplifies the process of integrating LCD and TFT displays into embedded systems.

Telelogic Rhapsody For Automotive
Rhapsody For Automotive, from Telelogic (STO:TLOG), is a SysML and UML solution designed and customized to address the needs of automotive systems engineers and software developers of automotive electronics. Rhapsody For Automotive is based on Telelogic’s Model Driven Development (MDD) environment.

Darnaw1 FPGA Module
Darnaw1 is a Spartan(TM)-3E FPGA module from Enterpoint. The module enables the use of FPGA technology in industrial and military sectors where the volume or assembly technology available precludes the use of BGA packaged FPGA devices. Encapsulating all the elements to support operation of the FPGA, the module has a simple to solder PGA pinout and operates with a single 3.3V power supply.

Enea dSPEED Platform
The dSPEED Platform, from Enea, is high availability platform designed to manage clusters of Digital Signal Processors (DSPs). dSPEED is a pre-integrated software platform for data plane processing targeting communications infrastructure line cards.

Aldec Active-HDL 7.3
Aldec, Inc. released Active-HDL 7.3 today. The 7.3 release includes multi-threaded HDL compilation, new waveform viewer, and expanded VHDL 2006 construct support. The new version improves performance in VHDL, Verilog, and mixed RTL compilation and simulation. Active-HDL is a mixed-language design creation, FPGA Project Management and simulation environment supporting VHDL, Verilog, SystemVerilog, and SystemC.

IAR YellowSuite for ColdFire Microcontrollers
IAR YellowSuite(TM) for ColdFire® microcontrollers integrates several tools to produce a working design in the shortest possible time. The development tools included in IAR YellowSuite for ColdFire microcontrollers consist of: IAR Embedded Workbench®, for building and debugging the application; IAR visualSTATE®, for design, validation, test and verification of the control logic; IAR PowerPac(TM) RTOS, file system and associated middleware; and an IAR KickStart Kit(TM), to test the application on real hardware.

Actel IGLOO Icicle Kit
Actel Corporation’ $99 Icicle(TM) Kit enables designers to easily and rapidly program, evaluate, and modify low-power IGLOO-based portable designs. The 1.4″ x 3.6″ Icicle evaluation board, which is powered by a lithium-ion battery, consumes less than one-seventh the power of competitive FPGA development solutions in a design the size of a small cell phone. Actel’s Icicle Kit allows designers to closely examine power consumption in various modes.

Mosaic Industries 24/7 Data Acquisition Wildcard
Mosaic Industries’ 24/7 Data Acquisition Wildcard is ideal for applications that require high resolution measurements. It accepts low level signals directly from transducers, amplifies and conditions them, and converts them with 24 bits of resolution with no missing codes. Mounted on any of Mosaic’s single board computers, it provides a high performance analog front end, offering exceptional resolution, stability, and noise rejection.

SANYO CCA-BC200 Automotive Backup Camera System
SANYO Electric Co. selected Altera Corporation’s (NASDAQ: ALTR) Cyclone® II FPGAs and Nios® II embedded processor for the CCA-BC200 Automotive Rear-View Backup Camera System. The Cyclone II FPGA featuring a Nios II embedded processor provides SANYO with a high-performance image-processing solution that minimizes distortion in wide-angle views and hard-to-interpret perspectives. The single-chip FPGA-based approach provides a more compact and reliable solution compared to digital signal processing (DSP) device-based approaches, which typically require two or more devices.

Analog Devices Precision Digital-to-Analog Converters
Analog Devices, Inc. (NYSE: ADI) recently introduced four new precision digital-to-analog converters (DACs) that significantly improve the reliability of industrial process control applications in harsh factory environments, including those operating under extreme temperatures or high compliance voltages. The offering includes four 12-bit to 16-bit single-channel DACs that integrate user-programmable current source and voltage output, making them ideally suited for factory process control, distributed control, and smart transmitter systems. By eliminating the need for bulky discrete analog circuitry and mechanical pin-strapped configurations, the DACs reduce board space by as much as 70 percent compared to competing solutions, enabling system design engineers to deliver more cost- and space-efficient industrial equipment.

Pentek Model 7141 Dual Multiband Transceiver
Pentek’s Model 7141 Dual Multiband Transceiver with FPGA is a complete software radio system for connection to HF or IF ports of a communications system and joins Pentek’s family of high-performance PMC/XMC transceiver modules. Model 7141 is an enhanced successor to Pentek’s Model 7140 transceiver, which is widely deployed by many customers for SIGINT, software radio, and communications applications. Pentek has significantly boosted analog performance in the Model 7141 so that the signal-to-noise ratio and the spurious free dynamic range are improved by 10 dB, when compared to many competitive products.

Physik Instrumente P-737 PIFOC Piezo-Z Stage
PI’s (Physik Instrumente) P-737 PIFOC Piezo-Z Stage is a high performance nanopositioning Z control system. The P-737 is specifically designed for biotech research microscopes utilizing deconvolution and 3D imaging techniques. The P-737 PIFOC specimen Z-stage features up to 250 µm travel, millisecond responsiveness, and nanometer precise motion under closed-loop control.

Across the Network – 2007.12.14

Altera Zero-Power MAX IIZ CPLDs
Altera Corporation (NASDAQ: ALTR) created the zero-power MAX® IIZ CPLD to address the power, package and price constraints of the portable applications market. Offering a resource advantage of up to six times the density and three times the I/Os compared to competing traditional macrocell-based CPLDs, MAX IIZ devices allow designers to meet changing functional requirements at the same or lower power while saving board space. MAX IIZ devices deliver the many benefits of CPLDs—including flexibility, faster time to market, and board-level integration—to handsets and other portable applications. Altera optimized MAX IIZ devices to offer the best combination of zero power, small package,and low cost.

Microchip 8-bit Flash Microcontrollers
Microchip Technology Inc. (NASDAQ: MCHP) recently announced 12 new high-performance, 8-bit Flash microcontrollers (MCUs). The PIC18F8723 high-memory, general-purpose family offers a rich peripheral set and performance of up to 10 MIPS. The PIC18F4553 family adds an integrated full-speed USB transceiver and 12 MIPS performance. Finally, the PIC18F8493 LCD microcontroller family offers integrated LCD drive capability for low-power display applications.

Actel LCD Control Solutions
Actel Corporation announced solutions for liquid crystal display (LCD) control applications. The new IGLOO Video Demo Board, LCD adaptor boards with LCD panels, the IGLOO Video Demo Kit (IVDK), and display-related reference blocks use the 5 microwatt (µW) IGLOO field-programmable gate arrays (FPGAs). The new offerings will be attractive to the power-sensitive designers of portable and handheld consumer, industrial, medical, automotive, and military devices that utilize small-to-medium LCD displays.

ToneCore DSP Developer Kit
The ToneCore DSP Developer Kit is a solution for digital signal processor (DSP) software developers who create custom sounds for guitarists. The kit enables third-party audio DSP developers with little or no electronic design experience to quickly and easily program audio effects modules for Line 6 ToneCore guitar pedals. Now with the Line 6 ToneCore DSP Developer Kit, all audio designers who write DSP code can create and sell a portable, affordable, battery-powered, stereo audio hardware product for musicians and audio enthusiasts. All it takes is a PC and the kit.

Lattice LatticeSC/M Supports Quad Data Rate
Lattice Semiconductor Corporation (NASDAQ: LSCC) announced FPGA-based support for Quad Data Rate (QDR) II/II+ memory devices. The LatticeSC(TM) and LatticeSCM(TM) FPGA families (LatticeSC/M) now support QDRII/II+ rates up to 750Mbps. The high-speed QDR II and QDR II+ memory controller IP (intellectual property) is implemented in Lattice’s low power Masked Array for Cost Optimization (MACO(TM)) structured ASIC technology.

Cimetrix EDAConnect Interface A Library
EDAConnect, from Cimetrix Incorporated (OTC: CMXX), is a client-side software library designed to assist integrated device manufacturers (IDMs) and third party software providers in creating applications that can utilize the rich data available via the new Interface A connectivity standards commonly known as Equipment Data Acquisition (EDA).

OneSpin Stand-Alone 360 EC-FPGA Equivalence Checker
OneSpin Solutions’ 360 EC-FPGA equivalence checker is now a stand-alone tool. Previously, 360 EC-FPGA was an extension of OneSpin’s 360 EC-ASIC equivalence checker. The stand-alone 360 EC-FPGA equivalence checker is the first sequential equivalence checking solution dedicated to and priced for the FPGA market. 360 EC-FPGA is the only equivalence checker to support all sequential optimizations performed by FPGA synthesis tools. The tool helps designers verify functionality without disabling the advanced synthesis optimizations vital to achieving functional, performance and cost goals.

Renesas SH-MobileL3V2, SH-MobileUL Application Processors
Renesas Technology recently announced two new application processors: SH-MobileL3V2 and SH-MobileUL. The SH-MobileL3V2 offers additional video formats, high-resolution video capture and enhanced functionality to control image quality. The small-package SH-MobileUL provides excellent cost performance and is suitable for use in popular mainstream mobile phone models. The new processors will accelerate the proliferation of advanced multimedia capture and playback on mobile phones and portable media players, enabling both advanced systems that offer higher image quality, as well as lower-priced systems that offer TV and other multimedia features.

Tensilica TRAX-PC Processor Trace
Tensilica®, Inc. added an optional full-speed, non-intrusive instruction trace capability to its configurable processor cores. Tensilica’s TRAX-PC processor trace capture macrocell is Nexus 5001 compatible and ideal for debugging complex, challenging real-time applications such as engine and motor control. Software control and use of the on-chip TRAX hardware is fully integrated into Tensilica’s Xplorer(TM) integrated design environment (IDE) so software engineers can easily develop and debug programs while using the TRAX-PC trace macrocell.

NEC NaviEngine1 LSI for Car Navigation Systems
NaviEngine®1, from NEC Electronics, is a single-chip system LSI solution optimized for car navigation systems. Based on four high-speed CPU cores using the ARM® MPCore(TM) technology with symmetric multi-processing (SMP), NaviEngine1 is capable of simultaneously processing multiple streams of information needed for car navigation systems, including vehicle location, driving directions, and navigation functions. The chip delivers high-speed parallel processing performance of up to 1920MIPS at 400 MHz. In addition, NaviEngine1 has impressive 2D and 3D graphics using the POWERVR SGX 535 graphics core by Imagination Technologies, and is the world’s first system LSI chip with built-in Serial ATA functions.

Precision Synthesis, Xilinx SmartGuide Combo
Precision® Synthesis, from Mentor Graphics Corporation (NASDAQ: MENT), combined with Xilinx® SmartGuide(TM) technology, reduces design time. Test results conducted jointly over the past year using Mentor’s Precision Synthesis tool and the Xilinx SmartGuide functionality show that users saved an average of 40% in mapping and place-and-route (P&R) time. The combined solution preserves unchanged portions of the design when making small changes, reducing overall design iteration time. Tests performed at Xilinx show that over 97% of the components went unchanged and quality of results (QoR) was maintained in the process. These results have also been verified by mutual customers.

Microwave Office 2007 Design Software Simulation Library
Applied Wave Research, Inc. (AWR®) recently released Microwave Office® 2007 design software simulation library. Microwave Office features NXP Semiconductor’s sixth-generation laterally-diffused metal oxide semiconductor (LDMOS) devices. The simulation library provides power amplifier (PA) and base station design engineers, as well as designers of worldwide interoperability for microwave access (WiMAX) and wireless broadcasting equipment with AWR- and NXP-proven large signal circuit simulation models.

VPN Firewall Upgrade System Patent
O2Micro® International Limited (NASDAQ:OIIM) (SEHK:0457) was issued 17 claims under Great Britain (GB) patent number 2,425,627 for its Field Programmable Gate Array (FPGA) IC upgrade system in VPN Firewall solutions.

Jasper GamePlan Verification Planner 1.2
Jasper Design Automation recently released GamePlan(TM) Verification Planner version 1.2. GamePlan is a powerful tool for generating and tracking verification plans. In version 1.2, GamePlan now includes the ability to import verification results. After an easy set-up that takes no more than a couple of hours, verification teams can begin reading verification results back into their test plan to efficiently track their verification progress. In addition, GamePlan also delivers improved search capabilities, active hyperlinks in analysis views for easy organization, and a new Undo/Redo feature for improved usability.

Altera Stratix III FPGA Features 1067 Mbps DDR3 Speed
Altera Corporation (NASDAQ: ALTR) Stratix® III FPGAs has achieved DDR3 memory interface speeds in excess of 1067 Mbps. The result is a 33% advantage in memory performance over competing FPGA solutions. The higher memory bandwidth enables new communications, computing, and video processing applications that were either previously impossible or required doubling the number of memory banks. Altera’s Stratix III FPGA family is the industry’s only FPGA to demonstrate full compliance to the JESD79-3 JEDEC DDR3 SDRAM standard, including the performance-critical read/write-leveling specification for maximum system performance.

Across the Network – 2007.12.07

Summit SMB137 Programmable Battery Charger IC
Summit Microelectronics’ SMB137 programmable battery charger IC was designed for mobile consumer electronics. Dual (USB or AC/DC) inputs and outputs (System or Battery) with CurrentPath(TM) automatic arbitration allow system operation with any input source, any battery charge state, or even missing battery. Proprietary TurboCharge(TM) technology yields dramatic reductions in charge time, power dissipation, and solution size compared to conventional charger solutions. The ultra-small solution size, combined with Micro-USB data/power support, enables ultra-thin devices with the convenience of USB battery charging.

IEEE 1588 Clock Synchronization for Lattice FPGA
Today Lattice Semiconductor Corporation (NASDAQ: LSCC) announced the availability of Industrial Ethernet Intellectual Property (IP) from Oregano Systems Design and Consulting. Oregano ported their IEEE 1588 IP core for clock synchronization over Ethernet to the LatticeXP(TM) and LatticeXP2(TM) FPGA families. Oregano’s IP core implements a popular IEEE standard that is used for many Industrial Ethernet applications to ensure that the various nodes in a network have synchronized real time clocks. The solution can be delivered as a standard IP core or Oregano can program it onto a LatticeXP or LatticeXP2 device and deliver it as an Application Specific Standard Product (ASSP).

NEC 15-inch LCD Modules
NEC LCD Technologies recently introduced two new 15-inch [38 centimeters (cm)-diagonal] amorphous-silicon color thin-film-transistor (TFT) liquid crystal display (LCD) modules with extended graphics array (XGA) resolution for industrial equipment such as factory automation controllers, measuring instruments, automatic teller machine (ATM) terminals, kiosks, and point-of-sale (POS) systems. The NL10276BC30-32 is a standard product with brightness of 250 candelas per square meter (cd/m2), while the NL10276BC30-33 has brightness of 350 cd/m2. Both modules conform to the Panel Standardization Working Group (PSWG) standards for 15-inch LCD modules.

Xilinx SPI-4.2 and SFI-4.1 Solutions
Xilinx Inc. (Nasdaq: XLNX) has developed solutions for the Optical Internetworking Forum (OIF) System Packet Interface (SPI) 4.2 and SerDes Framer Interface (SFI) 4.1 standards, the industry’s highest performance channelized packet interfaces. Xilinx’s solutions are based on Virtex(TM)-5 LXT FPGAs and feature the ML550 hardware verification board, SPI-4.2 LogiCORE(TM) IP, and SFI-4.1 reference design. Verified across multiple FPGA platforms, the solutions accelerate the design cycle of wired networking systems that require OC-192 (10 Gbps), multiple OC-48 (2.5 Gbps) or 10 Gbps Ethernet interfaces, resulting in much faster time-to-market than competing solutions.

STMicroelectronics LIS331 Motion Sensors
STMicroelectronics (NYSE: STM) introduced a new generation of ‘nano’ three-axis linear accelerometers. The low-power MEMS sensors provide complete output flexibility and embedded smart features. ST’s new 3-axis motion sensors represent a significant step forward in the product’s miniaturization. The 3x3x0.9mm plastic package addresses the space and weight constraints of portable electronic devices. The LIS331 accelerometers deliver high performance at low power consumption and their ultra-compact robust design provides very high immunity to vibration and shock survivability up to 10,000g.

Webinar: How to Quickly Design a Low-Cost ASIC
NEC and Tensilica are sponsoring a webinar on how to quickly design low-cost custom logic. The webcast will take place on Thursday, December 6th at 11 am Pacific (2:00 pm Eastern). The seminar will focus on designing low-cost ASICs using synthesizable 200-megahertz (MHz) 32-bit controllers.

TI TMS320C6452 Digital Signal Processor
Texas Instruments Incorporated (TI) (NYSE: TXN) recently announced the availability of the TMS320C6452 digital signal processor (DSP). The DSPs are designed to optimize price and performance for today’s process intensive multi-channel infrastructure and medical imaging systems. With a more than 30% price reduction over TI’s popular TMS320C6415T DSPs, the new code compatible 900 MHz C6452 DSP allows designers to quickly and easily migrate their designs from the widely deployed C641x based products.

Xilinx SpeedWay Workshops
Avnet Electronics Marketing announced a new series of SpeedWay Design Workshops(TM) featuring Xilinx® technology. The workshops are available in locations across the U.S. through March 2008.

GreenPeak Battery-Free Wireless Communication Devices
GreenPeak Technologies recently introduced new products for ultra-low-power wireless sense and control networks. GreenPeak’s new wireless communication devices leverage three key technologies that enable it to operate in a battery-free environment without cabling. The first is an ultra-low-power wireless transceiver and sensor interface design with efficient power-up and power-down modes that dramatically reduce power consumption. Second is an energy harvesting interface that enables the modules to utilize power provided by e.g. external solar, electromagnetic, and piezo-electric transducers. Third is a mesh technology that enables designers to create extended sensor networks without the need for battery-powered or cabled routing nodes. This innovative mesh technology is also self-forming and self-healing, making it easy and inexpensive to install.

Microtronix ViClaro III Video IP Development Kit
Microtronix, with the help of Altera, recently developed the ViClaro III HD Panel Display Interface – Video IP Development Kit. The ViClaro III kit helps high-definition (HD) video display designers build highly integrated, next-generation HD 1080p, 100-/120-Hz frame rate conversion television sets or panel display systems. The ViClaro III kit, which uses the Cyclone III FPGA as its engine, provides a comprehensive engineering design and evaluation platform. With the kit, designers can efficiently develop video-processing IP algorithms to support an array of display applications providing superior picture quality.

ARM RealView Profiler
ARM (LSE:ARM) (Nasdaq:ARMHY) recently launched their RealView(R) Profiler, which is a tool for non-intrusive analysis of software performance and code coverage of real system workloads running over minutes, hours, or days. Using the tool, developers can typically improve the performance of their application by more than 20%, while at the same time reducing ROM size requirements by a similar amount. The RealView Profiler also includes comprehensive analysis of both statement and branch code coverage, enabling software testing to achieve and demonstrate 100% code coverage to ensure the highest levels of software validation.

Programmable Solutions India 2007
Xilinx, Inc. (Nasdaq: XLNX) and CG-CoreEl will host Programmable Solutions India 2007 on December 11, 2007 in Bangalore and December 13, 2007 in Hyderabad. The events offer a full-day, complimentary line-up of keynotes, presentations, demonstrations and solution centre exhibits at each location to showcase industry-leading programmable solutions. Attendees will learn about silicon, IP, software, solutions and services from Xilinx and its network of solution providers, including Avnet, Nu Horizons, Agilent Technologies, Mentor Graphics, Wind River, iWave, Synplicity, and Nital.

GE Fanuc CC11, CL11 Single Board Computers
GE Fanuc Embedded Systems recently introduced their CC11 and CL11 3U CompactPCI single board computers. The SBCs feature a choice of Intel® Celeron® M (1.06 GHz), Core(TM) Duo (up to 2.0 GHz) or Core(TM)2 Duo (1.5 GHz) processors and up to two Gigabytes of onboard DDR2 SDRAM, each can be ordered as either a system slot or non system slot device. Designed for a broad range of applications including automation, transportation, imaging, medical and robotics, the CC11 and CL11 take maximum advantage of the benefits of CompactPCI in its 3U form factor, delivering high performance in a small, lightweight package. Each board is available in extended temperature range (-40° C to +75° C) forms to enable installation in environments that would otherwise be unsuitable.

Tips for FPGA Timing Closure

Lattice is offering a webcast for FPGA designers. The one-hour event will take place Wednesday, March 28, 2007 at 11:00 am Pacific time (2:00 pm Eastern). Here’s the webinar blurb:

FPGA designers often find themselves squeezing every last bit of performance out of the least expensive, slowest speed grade, device available. In this presentation, Lattice Semiconductor provides practical advice on how a combination of RTL style, constraints, and optimization options can be applied to produce the most efficient FPGA implementation.

One participant who attends the live broadcast and fills out the feedback form will receive either an ispLEVER Development Tool for Lattice programmable logic design or a spaceship.

Troy Scott is a marketing specialist at Lattice Semiconductor Corporation. He has more than 15 years experience in the EDA and semiconductor industry. Troy’s background includes HDL synthesis and simulation, hardware emulation, and IP evaluation and marketing. Troy holds a BSCE from Oregon Institute of Technology and a Graduate Certificate in Computer Architecture and Design from Portland State University.

More info »

Altera FPGAs Drive SDR at Software Radio Summit

At the Software Radio Summit, Altera will be featuring:

  • SDR waveform design flow for Software Communication Architecture (SCA), Common Object Request Broker Architecture (CORBA) and Serial RapidIO(TM) applications
  • Demos of WiMAX waveforms used by military systems developers

Altera’s SDR experts will discuss:

  • Addressing size, weight and power (SWaP) requirements with Altera’s new 65-nm Stratix(R) III FPGA family
  • Using Programmable Power Technology to address high-performance SDR applications
  • Altera’s Enhanced COTS strategy focused on Mil/Aero system development
  • Altera’s partner ecosystem supporting the SDR marketplace

A tutorial, “Achieving Integrated SDR Solutions Using Programmable Logic” will be presented Tuesday, February 20, 2:30–5:30pm.

Software Radio Summit and SDR University
February 20–23, 2007
Sheraton Premier Hotel at Tyson’s Corner
Tyson’s Corner, VA

free trade publications

More information: Altera at the Software Radio Summit »

Altera Stratix III FPGA Web Seminars

Altera has a two web seminars about its new 65-nm high-end Stratix(R) III FPGA family:

Overview of Altera’s 65-nm Stratix III FPGAs
This 15-min QuickCast discusses how Altera’s Stratix III 65-nm high-end FPGAs meet your business and technical requirements. In this QuickCast, you’ll learn more about:

  • Altera’s methodology for delivering programmable logic solutions to meet the next-generation business and technical
  • requirements of industry leading customers around the world
  • Technology innovations, including Programmable Power Technology, higher performance and fast interconnects
  • The risk-free path from Stratix FPGAs to HardCopy(R) structured ASIC
  • Quartus II development tools to improve productivity

Target Audience:

  • System Architects
  • Engineering and Technical Managers
  • Engineering Executives

Using Stratix III FPGAs to Achieve Higher Performance Systems with Lower Power Net
Not all logic paths are created equal, so why do you need to supply the same currents to the slow paths as you do the fast ones? Found only in Altera’s Stratix III 65-nm FPGAs, Programmable Power Technology delivers maximum power when needed to critical paths in your design and low power everywhere else. This revolutionary logic array block (LAB)-based feature provides an incredible 50 percent power saving and 25 percent performance improvement over the previous generation FPGAs.

Programmable Power Technology is one of the many innovative features built into Altera’s Stratix III devices that were developed in collaboration with industry leading customers around the world. Learn how these features, along with performance optimizing Quartus II development tools and EDA synthesis support, supply complete solutions and enable you to design your next-generation high-end system with confidence.

In this online seminar, you will learn more about Stratix III FPGAs:

  • Logic-rich, DSP- and memory-rich, and transceiver-based device variants
  • Customer recommended features and benefits for next-generation system designs
  • Adaptive logic module (ALM) architecture
  • Development tools and methodology

Target Audience:

  • System Architects
  • Embedded System Design Engineers
  • FPGA Developers
  • Engineering and Technical Managers

free Military & Aerospace Electronics

More information »

Embedded Design with LatticeMico32 Open, Free 32-bit Soft Processor

Lattice will be giving away an ispLEVER Development Tool for Lattice FPGA and CPLD design to one participant of their upcoming web seminar, Embedded Design with LatticeMico32 Open, Free 32-bit Soft Processor.

The one-hour webcast will take place on Wednesday, October 18, 2006 at 11:00 am Pacific time (2:00 pm Eastern). In the online seminar, you will learn how to use the new LatticeMico32 open, free 32-bit soft processor. The LatticeMico32 provides the performance and flexibility suitable for a wide variety of markets. Lattice’s unique license allows users to ensure that their proprietary designs remain proprietary and allows the implementation and distribution of hardware without the need for a separate license agreement.

free computer magazines

This comprehensive 32-bit Harvard, RISC soft processor solution that is:

  • Completely Free
  • Open Source and Portable
  • Based on Eclipse C/C++ Development Tools
  • Well Documented
  • High-Performance and Easy-to-Use
  • FPGA-Optimized

Actel’s Flash FPGAs Defeat Attacks by Earth

According to a comprehensive third-party investigation, Actel’s flash-based field-programmable gate arrays (FPGAs) are immune to configuration upsets caused by high-energy neutrons naturally generated in the earth’s atmosphere. The study also determined that advances in semiconductor manufacturing technology have had a detrimental impact on the reliability of SRAM-based FPGAs, making them more vulnerable to neutron-induced configuration loss, a major concern for designers of high-reliability systems such as medical, telecommunications, storage area network (SAN), military and avionics systems. Configuration loss also poses a threat to the quality of high-volume consumer and automotive applications. The study was conducted in December 2005, by iRoC Technologies at the Los Alamos Neutron Sciences Center (LANSCE) at Los Alamos National Laboratory in New Mexico.

The iRoC results demonstrate that neutron-induced configuration upsets pose a real threat to product quality and reliability, an important consideration as semiconductors proliferate into more of the high-reliability systems people depend on every day. Because Actel’s flash-based technologies are inherently immune to these functionality changes, designers can count on the ProASIC3 FPGAs and Fusion Programmable System Chips to protect design integrity, even as process geometries shrink. By eliminating neutron-based firm errors as a source of field failures, Actel allows designers of consumer products to meet stringent price and power goals without compromising product quality.

Source: Actel

EE Times FPGA Users Survey

According to the EE Times 2006 EDA Users Survey, FPGA complexity and speed are rapidly increasing, and as a result, FPGA designers are confronting many of the same issues — and adopting some of the same tools — as their counterparts in ASIC and IC design. Here are some excerpts:

Engineers are expecting average gate counts of around 4 million within two years. While meeting timing budgets is the prime concern today, our North American FPGA respondents, just like the respondents to the ASIC portion of the survey, said that leakage current is getting notably worse as silicon geometries shrink.

There are other ways in which the FPGA survey results mirrored those in the ASIC survey. In both cases, EDA budgets are rising faster in Asia. In both surveys, designers are most satisfied with the accuracy of their EDA tools, and least satisfied with pricing and interoperability. And in both surveys, North American designers were generally more satisfied with tools and vendors than respondents to EE Times’ 2005 survey, which focused on North America only.

The 2006 survey also shows that tools and technologies from the ASIC world are seeing broader acceptance. Huge majorities are using FPGA synthesis, HDL simulation and FPGA floor planning, and there’s growing interest in hardware/software co-design, power analysis, SystemVerilog and C-language synthesis.

Source: EE Times