Mentor Graphics has expanded their set of tools and technologies included in the TSMC Reference Flow 10.0. The expanded Mentor track supports advanced functional verification for complex ICs, netlist-to-GDSII implementation for 28nm ICs, tighter integration with the ubiquitous Calibre physical verification and DFM platform, and tools for layout aware test failure diagnosis. The improved Mentor track also addresses low power design with Mentor tools for functional verification, IC implementation, and IC testing.
Taiwan Semiconductor Manufacturing Company (TSMC) released the first interoperable process design kit (iPDK) for advanced technology. The kit is fully validated on TSMC’s 65 nanometer (nm) process. TSMC unified iPDK works across multiple OpenAccess-based EDA design environments, eliminating the need for multiple proprietary PDKs, and enabling full reuse of design data between different custom IC design toolsets. The iPDK initiative is supported by all major EDA vendors including Cadence, Magma, Mentor Graphics, Springsoft, and Synopsys.
Semiconductor Manufacturing International Corporation (SMIC) has successfully completed their first 45-nanometer high performance (GP, generic process with high performance) yield lot. The high-speed, high performance 45nm GP technology integrates a silicon germanium stress module into the design. The process enables the device to run faster and make it ideal for system-on-chip, graphics and network processors, telecommunications, and wireless consumer products. SMIC’s 45nm GP technology is supported by a proven design-in SPICE model and in-house design IP capability that enables customers to begin prototype product design and plan for early time-to-market.
More info: SMIC
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) introduced version 4.0 of their 65-nanometer (nm) RTL-to-GDSII reference design flow. The reference flow features support for the Synopsys Eclypse Low Power Solution and IC Compiler Zroute technology. The joint solution gives IC engineering teams a proven reference flow to advance SoC designs targeting SMIC’s 65nm process technology and Synopsys’ low power and DFM technologies. The SMIC-Synopsys Reference Flow 4.0 is available now.
X-FAB Silicon Foundries developed the first foundry process for the production of integrated Hall sensor ICs in 0.18 micrometer technology. The XH018 low-power CMOS process enables the combination of Hall sensor elements with high-voltage devices and Non-Volatile Memory (NVM) options. X-FAB’s XH018 technology for integrated Hall sensor solutions is available today. It comes with comprehensive design support including characterization data and layout examples.
LFoundry introduced a process design kit (PDK) for A/MS electronic designs. The PDK was developed using Tanner EDA’s HiPer Silicon™ software. LFoundry is providing Tanner EDA users with the LF150 modular 0.15 µm Low Power and RF CMOS process that features up to six levels of aluminium interconnect, a polymide passivation and I/O voltages of 1.8V, 3.3V and 5.0V. Optionally a MiM capacitor is also available. The process is based on a 0.15 µm CMOS proven technology and offers excellent versatility for ASIC designers. In addition to schematic and layout libraries for full custom analog design, LFoundry provides a cell library with standard cells and periphery cells.
Taiwan Semiconductor Manufacturing Company announced the iRCX interoperable electronic design automation (EDA) data format for TSMC 65nm and 40nm processes. iRCX format unifies interconnect modeling data delivery, ensures data integrity and interpretation. EDA tools which support iRCX format will be able to receive accurate interconnect modeling data from the iRCX files developed and supported by TSMC. Interconnect related EDA applications, including place and route, RC extraction, electromigration analysis, power integrity analysis, and electromagnetic simulation are to benefit from iRCX.
More info: TSMC
Semiconductor Manufacturing International Corporation (SMIC) announced a set of 65-nanometer low leakage process IPs. SMIC’s new 65nm IPs includes a set of six memory compilers, which enable the intelligent and rapid generation of memory blocks in bulk and on the fly. The compilers feature memories optimized for very high performance and also optimized for performance and area. The silicon validation is undergoing. The 65nm IP portfolio can be used to design a wide range of consumer applications such as mobile phones, personal media players, GPS, DTV, set-top boxes, and mobile storage devices.
SMIC released three preliminary versions of their 65-nanometer standard cell libraries. The libraries include a high performance Very High Speed (VHS) library, a density and performance optimized High Speed (HS) library, and a power management kit (PMK) for the High Speed (HS) library. The new 65nm standard cell libraries were designed to meet industry standards and closely follow design for manufacturing (DFM) rules. SMIC also has a High Density (HD) library under development that will be optimized for high density and low power.
Taiwan Semiconductor Manufacturing Company, Ltd. (TSE: 2330, NYSE: TSM) recently announced the Unified Design For Manufacturing (UDFM) architecture. UDFM targets 32nm process technology and smaller geometries and improves yields, lowers design costs, and accelerates time-to-market and time-to-volume. UDFM provides a unified, encapsulated access to TSMC foundry data and was developed in collaboration with EDA vendors and other design infrastructure partners.
The TSMC UDFM architecture includes a new DFM Design Kit (DDK) that encapsulates an embedded DFM software engine with an interoperable API in addition to the process-related DFM data and models. UDFM brings an exact copy of TSMC’s factory tool chain and process models into IC design tool chains, providing chip designers with deeper access into more of TSMC’s manufacturing data than ever before. This “copy exact” method compensates for increasing manufacturing variances in advanced process technologies, radically improves design alignment between simulated hotspots and actual manufacturing hotspots, and delivers timely accuracy to the design ecosystem. The new DFM architecture handles very large DFM dataset and design complexity, resulting in reduced design cycle time and faster time-to-market and volume.
More info: TSMC