EDA Blog » Foundry

Cadence, Samsung Foundry Develop DFM Flows for 32nm, 28nm, 20nm Chip Design

Ken Cheung — Mon, 06 Feb 2012 19:08:51 +0000

Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.

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Cadence Library Characterizer Reference Kit for TSMC Cell Libraries

Ken Cheung — Mon, 17 Oct 2011 15:52:01 +0000

Cadence Design Systems and TSMC teamed together on a library characterization reference kit. The Cadence Library Characterizer (Altos Liberate) reference kit for TSMC’s standard cell libraries is now available to TSMC customers for download on TSMC-Online. As a result, TSMC customers can now leverage the same technology used in-house at TSMC with the same setup and constraints, helping them address the specific design challenges created through changes to their standard cell libraries.

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Mentor Graphics Calibre YieldEnhancer Supports SmartFill Functionality

Ken Cheung — Wed, 14 Sep 2011 16:01:36 +0000

Mentor Graphics is teaming with TSMC on a SmartFill solution for TSMC’s manufacturing processes starting at 65nm. As a result of the collaboration, Calibre YieldEnhancer product will support SmartFill functionality. The analysis and automatic filling capabilities of the SmartFill solution enables engineers to achieve IC fill constraints with minimal impact on circuit performance in a single pass without manual customization or modification.

Synopsys 28nm Design Solutions for TSMC Reference Flow 12.0

Ken Cheung — Fri, 27 May 2011 16:08:32 +0000

Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of TSMC’s latest 28-nm design rules and models within Synopsys’ Galaxy Implementation Platform.

Mentor Graphics and Dongbu HiTek Technology Design Kits for Analog BCDMOS

Ken Cheung — Mon, 10 Jan 2011 18:51:14 +0000

Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.

Magma, Virage Logic Reference Flow for GLOBAL FOUNDRIES 65nm Process

Ken Cheung — Wed, 16 Jun 2010 01:24:50 +0000

Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage Logic upon request.

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X-FAB XO035 Process for Blu-ray and Optical Data Communication

Ken Cheung — Tue, 19 Jan 2010 07:59:26 +0000

X-FAB Silicon Foundries announced the XO035 0.35 micrometer process. The XO035 foundry process is optimized for Blu-ray and high-speed optical data communication applications. XO035 includes X-FAB’s blue PIN module. The integration of the PIN diode into the 0.35 micrometer CMOS environment enables the design of high-performance photo detectors. The XO035 process is available now.

Process Design Kits for UMS PH15 and PH25 GaAs MMIC Foundry Processes

Ken Cheung — Mon, 07 Dec 2009 17:39:59 +0000

AWR and United Monolithic Semiconductors (UMS) introduced enhanced process design kits (PDKs) for the UMS PH15 and PH25 advanced gallium arsenide (GaAs) foundry processes. The enhanced PDKs enable designers to take full advantage of the process capabilities of UMS within AWR’s 2009 Microwave Office design suite including its latest technologies such as iNets, AC0E, AXIEM, and ICED DRC. Engineers can also take advantage of the fact that the PDKs are now release-independent from AWR’s own software upgrade cycle. PDKs from UMS are available to active customers of the UMS foundry and AWR software.

More info: AWR

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IMEC-TSMC Innovation Incubation Alliance

Ken Cheung — Tue, 06 Oct 2009 16:50:39 +0000

IMEC and TSMC is forming an Innovation Incubation Alliance to create a platform for enabling the development of product solutions using emerging More-than-Moore technology options. Integrating extra functionalities with foundry CMOS enables customers to compete in emerging markets. By combining IMEC’s expertise in design and technology R&D with TSMC’s excellence in high-volume manufacturing, customers will benefit from an early access to new More-than-Moore technologies and rapid transition to volume manufacturing for their next generation electronic products.

WIN/AWR Process Design Kit for H2W PH50-00 GaAs Foundry Process

Ken Cheung — Wed, 30 Sep 2009 17:27:48 +0000

AWR and WIN Semiconductors introduced the WIN/AWR H2W PH50-00 process design kit (PDK). The PDK for the WIN PH50-00 GaAs enhancement / depletion-mode pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) foundry process is the latest in AWR’s series of PDKs available for monolithic microwave integrated circuit (MMIC) designers. The AWR/WIN PH50-00 PDK is available now for use within AWR’s Microwave Office v2009 software. All AWR/WIN PDKs are distributed by WIN Semiconductor and available free of charge to qualifying customers.