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'Foundry' Category Archive

Cadence Library Characterizer Reference Kit for TSMC Cell Libraries

Posted by Ken Cheung in EDA Tools,Foundry on Monday, October 17, 2011

Cadence Design Systems and TSMC teamed together on a library characterization reference kit. The Cadence Library Characterizer (Altos Liberate) reference kit for TSMC’s standard cell libraries is now available to TSMC customers for download on TSMC-Online. As a result, TSMC customers can now leverage the same technology used in-house at TSMC with the same setup [...]

Mentor Graphics Calibre YieldEnhancer Supports SmartFill Functionality

Posted by Ken Cheung in EDA Tools,Foundry on Wednesday, September 14, 2011

Mentor Graphics is teaming with TSMC on a SmartFill solution for TSMC’s manufacturing processes starting at 65nm. As a result of the collaboration, Calibre YieldEnhancer product will support SmartFill functionality. The analysis and automatic filling capabilities of the SmartFill solution enables engineers to achieve IC fill constraints with minimal impact on circuit performance in a [...]

Synopsys 28nm Design Solutions for TSMC Reference Flow 12.0

Posted by Ken Cheung in Design Flow,Foundry on Friday, May 27, 2011

Synopsys introduced 28nm design solutions that integrate manufacturing compliance and system-level prototyping with TSMC Reference Flow 12.0. The extended Reference Flow 12.0 reduces time-to-market and speeds time-to-volume using TSMC’s 28-nm process technology. The design enablement solution features virtual prototyping and high-level synthesis linked to TSMC’s advanced processes, expanded manufacturing compliance capabilities and full support of [...]

Mentor Graphics and Dongbu HiTek Technology Design Kits for Analog BCDMOS

Posted by Ken Cheung in Design Flow,Foundry on Monday, January 10, 2011

Mentor Graphics and Dongbu HiTek rolled out a series of Technology Design Kits (TDKs). The Technology Design Kits support Dongbu HiTek’s analog-intensive BCDMOS process technologies. The TDKs used with IC Station (Mentor’s Custom IC Design Flow solution) will seamlessly accelerate BCDMOS chip designs from system specifications to post-layout verifications.

Magma, Virage Logic Reference Flow for GLOBAL FOUNDRIES 65nm Process

Posted by Ken Cheung in Design Flow,Foundry on Tuesday, June 15, 2010

Magma Design Automation, GLOBALFOUNDRIES, and Virage Logic introduced a Unified Power Format (UPF)-compliant RTL-to-GDSII reference flow. The automated, comprehensive solution streamlines the design and manufacture of ICs that use Virage Logic’s intellectual property (IP) and are manufactured in GLOBALFOUNDRIES’ 65LPe 65-nanometer (nm) low-power process technology. The reference flow is available from Magma, GLOBALFOUNDRIES and Virage [...]

X-FAB XO035 Process for Blu-ray and Optical Data Communication

Posted by Ken Cheung in Foundry on Tuesday, January 19, 2010

X-FAB Silicon Foundries announced the XO035 0.35 micrometer process. The XO035 foundry process is optimized for Blu-ray and high-speed optical data communication applications. XO035 includes X-FAB’s blue PIN module. The integration of the PIN diode into the 0.35 micrometer CMOS environment enables the design of high-performance photo detectors. The XO035 process is available now.

Process Design Kits for UMS PH15 and PH25 GaAs MMIC Foundry Processes

Posted by Ken Cheung in Foundry on Monday, December 7, 2009

AWR and United Monolithic Semiconductors (UMS) introduced enhanced process design kits (PDKs) for the UMS PH15 and PH25 advanced gallium arsenide (GaAs) foundry processes. The enhanced PDKs enable designers to take full advantage of the process capabilities of UMS within AWR’s 2009 Microwave Office design suite including its latest technologies such as iNets, AC0E, AXIEM, [...]

IMEC-TSMC Innovation Incubation Alliance

Posted by Ken Cheung in Foundry,Research on Tuesday, October 6, 2009

IMEC and TSMC is forming an Innovation Incubation Alliance to create a platform for enabling the development of product solutions using emerging More-than-Moore technology options. Integrating extra functionalities with foundry CMOS enables customers to compete in emerging markets. By combining IMEC’s expertise in design and technology R&D with TSMC’s excellence in high-volume manufacturing, customers will [...]

WIN/AWR Process Design Kit for H2W PH50-00 GaAs Foundry Process

Posted by Ken Cheung in Foundry,Models, Simulations on Wednesday, September 30, 2009

AWR and WIN Semiconductors introduced the WIN/AWR H2W PH50-00 process design kit (PDK). The PDK for the WIN PH50-00 GaAs enhancement / depletion-mode pseudomorphic high electron mobility transistor (pHEMT) and heterojunction bipolar transistor (HBT) foundry process is the latest in AWR’s series of PDKs available for monolithic microwave integrated circuit (MMIC) designers. The AWR/WIN PH50-00 [...]

X-FAB TheKit Process Design Kits for Cadence Virtuoso IC 6.1

Posted by Ken Cheung in Foundry on Tuesday, September 22, 2009

X-FAB Silicon Foundries introduced TheKit process design kits (PDK). TheKit is based on the Cadence Design Systems Virtuoso IC 6.1 custom design platform and SKILL programming language. TheKit is available for all of X-FAB’s process technologies from 1.0 um down to 0.18 um. The process design kit offers a smooth and easy migration from existing [...]

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