One of the major issues to IC design now and going forward is manufacturing process variations impacting product yield. Achieving high yield means functionally working die while delivering high performance and rapidly getting to market. The typical design flow has inherent issues and as a result, the design for yield (DIY) centric design flow has been developed.
Synopsys is offering 20nm process technology support for the TSMC 20nm Reference flow. The 20nm process offers measurable power, performance and area benefits. TSMC and Synopsys have collaborated closely from the very early stages of 20 nanometer process development to address the challenges of 20nm design. The results of this collaboration will help designers maximize the benefits of the 20nm process to deliver the designs predictably and on time.
Synopsys’ unified mixed-signal IC design solution has been qualified for TowerJazz’s power management analog/mixed-signal reference design flow (Reference Flow 2.0) and 180-nanometer (nm) Power Management (PM) interoperable process design kit (iPDK). Synopsys’ tool suite, the foundry iPDK and reference design flow are verified to seamlessly work together to enable designers to quickly become productive.
Synopsys DesignWare IP is now available on the SMIC 40-nanometer low-leakage (40LL) process. The DesignWare IP for the SMIC 40LL process includes USB 2.0 picoPHY, HDMI 1.4 TX PHY, DDR multiPHY, MIPI D-PHY, PCI Express 2.0/1.1 PHY, SATA 1.5Gb/s/3Gb/s PHY, SATA 6Gb/s PHY, and select audio codecs and data converter IP. DesignWare USB 3.0 PHY, HSIC PHY, data converters and AFE for LTE and Wi-Fi, and Embedded Memory and Logic Library IP are available for early adopters. Availability for the DesignWare HDMI RX PHY and DDR3/2 PHY IP is planned for Q4 2012.
Synopsys and Semiconductor Manufacturing International Corporation (SMIC) released version 5.0 of their 40-nanometer RTL-to-GDSII reference design flow. The SMIC-Synopsys Reference Flow 5.0 enables IC designers to accelerate their designs into manufacturing through the combination of SMIC’s 40nm process technology and Synopsys’ technology-leading design solutions. The SMIC-Synopsys Reference Flow 5.0 is available now.
Cadence Design Systems and Samsung Electronics teamed together on a 20-nanometer design methodology. Their 20nm digital design methodology features double patterning technology for joint customer deployment and internal test chips. The new design methodology enables design at 20 nanometers and future process nodes. It is ideal for mobile consumer electronics.
Synopsys introduced version 1.4 of their DesignWare HDMI (High-Definition Multimedia Interface). The PHY IP is available in advanced 28 nanometer processes for multiple foundries. Availability of DesignWare HDMI 1.4 IP on multiple 28nm processes ensures designers have access to the high-quality, silicon-proven IP so they they can quickly incorporate the latest audio and video functionality into next-generation mobile and digital home devices. DesignWare HDMI 1.4 PHY IP is available now in 90nm to 28nm process nodes. The DesignWare HDMI 1.4 TX and RX digital controllers are also available now.
Cadence Design Systems and Samsung Foundry teamed together to create a design-for-manufacturing infrastructure to produce complex chips. Cadence worked closely with Samsung Foundry to integrate their robust DFM suite. The resulting flows and underlying infrastructure provide a significant competitive edge by enabling engineers to meet tight deadlines while reducing the risk of costly errors.
Cadence Design Systems and TSMC teamed together on a library characterization reference kit. The Cadence Library Characterizer (Altos Liberate) reference kit for TSMC’s standard cell libraries is now available to TSMC customers for download on TSMC-Online. As a result, TSMC customers can now leverage the same technology used in-house at TSMC with the same setup and constraints, helping them address the specific design challenges created through changes to their standard cell libraries.
Mentor Graphics is teaming with TSMC on a SmartFill solution for TSMC’s manufacturing processes starting at 65nm. As a result of the collaboration, Calibre YieldEnhancer product will support SmartFill functionality. The analysis and automatic filling capabilities of the SmartFill solution enables engineers to achieve IC fill constraints with minimal impact on circuit performance in a single pass without manual customization or modification.