Cadence Design Systems has issued a call for papers to be presented at MemCon 2013. Cadence is seeking presentations and papers on topics that illustrate users’ knowledge and expertise in memory design and architecture. The deadline for paper abstract submission is May 30, 2013. The MemCon conference showcases the thought leaders driving advances in memory technology. The event will take place August 6, 2013 at the Santa Clara Convention Center.
XJTAG will hold a free boundary scan training workshop at the UK’s Manufacturing Technology Centre (MTC). The workshop will provide an introduction to boundary scan and to show how the debug, test and programming process can be used throughout the product life cycle. The XJTAG workshop will take place Wednesday, June 12, 2013 in Coventry.
HEM Data will be conducting a SAE seminar. The event will focus on the newer approach of obtaining data from the in-vehicle network for automotive, heavy duty, off-road, and marine applications. The title of the seminar is: Acquiring and Analyzing Data from Sensors and In-Vehicle Networks. The SAE seminar will take place May 15-16, 2013 in Troy, Michigan.
Analog Devices, Xilinx, and MathWorks announced a series of design conferences for analog, mixed-signal and embedded systems engineers. During the conference, attendees will learn how MATLAB and Simulink can be used to develop, model and deploy high-performance signal processing systems. Design Conference 2013 will take place in the United States, Germany and China. Avnet, Digilent and 4DSP, sponsors of the U.S. conferences, will showcase their industry-leading solutions based on ADI’s analog and mixed-signal technologies.
AWR, Cree, and Microwave Journal will host a webinar next week. The webcast will help power amplifier (PA) designers learn more about the design of Class F, inverse Class F, and continuous Class F power amplifiers using Cree GaN HEMTs and AWR’s Microwave Office circuit design software. The online seminar will take place Tuesday, March 26 at 11 am EDT. The event is titled: The Design of Class F, Inverse Class F and Continuous Class F Power Amplifiers using Cree GaN HEMTs and AWR’s Microwave Office.
DATE 2013 will take place March 18-22 at the Alpexpo Conference Center in Grenoble, France. The conference features keynotes, tutorials, workshops and exhibition. DATE 2013 will be opened by plenary keynote speakers Dr. Benedetto Vigna, Vice President of STMicroelectronics, who will give a presentation addressing Smart Systems for the Internet of Things, and professor Massoud Pedram from the University of Southern California, who will talk on Creating a Sustainable Information and Communication Infrastructure.
Cadence Design Systems will hold their CDNLive Silicon Valley User Conference on March 12 and 13 in Santa Clara. CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.
The International Symposium on Quality Electronic Design will take place Monday, March 4 through Wednesday, March 6, 2013 at TechMart, Santa Clara. The event includes free admission to select presentations and exhibits. ISQED 2013 conference includes 22 technical sessions, close to one hundred papers, keynotes, tutorials, workshops and exhibits. The event will focus on the latest innovations and developments in electronic design and manufacturing.
The 2013 Design and Verification Conference (DVCon) will feature twelve technical sessions, ten tutorials, a poster session with over twenty posters being presented, and two panels throughout the conference. DVCon is a conference for the discussion of the functional design and verification of electronic systems. The event is sponsored by Accellera Systems Initiative, an independent, not-for profit organization dedicated to creating design and verification standards. VCon will take place February 25 – 28 at the DoubleTree Hotel in San Jose, California.
Calypto Design Systems will host two webinars next month. The online seminars will educate designers on the latest in high level synthesis (HLS) and power optimization techniques for RTL-based designs. The titles of the webcasts are Minimizing RTL Power through Sequential Analysis, and A Practical Comparison Between C++ and SystemC for High Level Synthesis.