Open Source VMM Methodology for SystemVerilog
Synopsys, Inc. (NASDAQ: SNPS) recently released the source code for its complete implementation of the proven VMM verification methodology for SystemVerilog, including the VMM Standard Library and VMM Applications, under the popular Apache 2.0 open source license. Synopsys' implementation of the VMM methodology, originally defined in the Verification Methodology Manual for SystemVerilog, was recently donated [...]
Free OCP-Conductor Professional Transaction Analysis Tool
Duolog Technologies is offering its OCP-Conductor Professional transaction analysis tool free of charge to members of OCP-IP. The Tool is a detailed OCP transaction viewer that enables fine-grained analysis of bus transactions. A complete transaction sequence can be traced from request to response along with a host of related information about the transaction, permitting instant, [...]
Revised IEEE 1647 Standard for the Functional Verification Language e
The IEEE recently approved a revision to IEEE 1647 Standard for the Functional Verification Language e. The e language was first ratified as a standard in 2006 and is a powerful high-level verification language for hardware designers. Over time the standard has continued to evolve and add many new technology advancements. The revision of the [...]
Sequence Design PowerArtist
PowerArtist, from Sequence Design, features the industry's fastest automated RTL power reduction – 10 to 50 percent or more depending on the design. Unlike approaches limited by design size, PowerArtist has run on a 15M gate design in four hours within a 12GB footprint. PowerArtist integrates with all standard design flows, including synthesis and formal [...]
Xyalis GTmask for Wafer Masks Building
Xyalis recently introduced GTmask, which is a fully integrated environment dedicated to complex wafer masks building. GTmask offers capabilities that meet mask teams' demands, covering wafer assembly and floorplanning for chip arrays, multi-project wafers and multi-layer reticles; CMP metal filling; automatic frame generation; and optimized GDSII and jobdeck files generation. GTmask is built upon Xyalis' [...]
Synopsys Zroute Multi-threaded Router
Zroute, from Synopsys, Inc. (NASDAQ: SNPS), is a new multi-threaded router fully integrated into IC Compiler. Zroute has been developed from the ground up to take full advantage of the newest multi-core microprocessor architectures and to solve emerging design for manufacturability (DFM) challenges in IC design. IC Compiler is Synopsys' comprehensive physical design solution.
Zroute's modern [...]
Magma Hydra Automated Floorplan Synthesis Tool
Hydra, from Magma Design Automation Inc. (Nasdaq:LAVA), is an automated floorplan synthesis and hierarchical design planning product with physical optimization capabilities that delivers superior predictability. Unlike existing floorplanning and prototyping tools, Hydra takes timing, power, congestion and area into consideration and generates an implementation-ready floorplan, reducing turnaround time of very large designs. Hydra is available [...]
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