Synopsys recently launched Formality Ultra, which is a new configuration of the Formality equivalency checking solution. Formality Ultra enables designers to reduce the time and effort required to implement ECOs. This increases schedule predictability and helps engineers close designs on time. The Synopsys tool gives designers the ability to implement more complex functional changes as engineering change orders rather than wait for the next derivative of the design.
Real Intent launched version five of their Meridian CDC tool. The new hierarchical CDC flow supports partitioned analysis of designs without sacrificing top-level full-chip precision for giga-scale sign-off. Meridian CDC’s hierarchical flow avoids the compromises found with abstract-modeling and the use of waivers in other products. Meridian CDC v5.0 will be available July 1, 2013. Pricing depends on product configuration.
Synopsys has extended their DesignWare Duet Embedded Memory and Logic Library IP to enable the optimized implementation of a broad range of processor cores. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum. The DesignWare HPC Design Kit will be available for leading 28-nm processes starting in July of this year.
Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.
Synopsys introduced the DesignWare ARC EM Starter Kit for the ARC EM family of embedded processor cores. The DesignWare ARC EM Starter Kit, ARC EM4 and ARC EM6 processor cores and associated development tools are available now. The DesignWare ARC EM4 and ARC EM6 processor cores are optimized for use in embedded and deeply embedded applications such as sensors, storage devices, appliances, consumer electronics, and battery-operated devices where high performance, small size and minimal power consumption are essential.
CommandFusion introduced the iViewer Lite iOS app. The mobile application helps DIY users and installers of smaller automation systems to create their own custom graphical user interfaces (GUIs). iViewer Lite is available on the Apple App Store for $49.99. The app is compatible with all iOS devices running an iOS version of 4.3 or higher.
Synopsys introduced the Virtualizer Development Kit for Renesas RH850 microcontrollers. The VDK accelerates software development, system integration and test for RH850-based automotive applications such as body, powertrain/hybrid and chassis/safety control. The new development kit seamlessly integrates into existing software development flows. The VDK makes it easy for engineering teams throughout the automotive supply chain to deploy and achieve higher levels of product reliability, reduce overall development cost and shorten design cycles. The VDK for Renesas RH850 MCU is available now.
Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.
Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.
Mentor Graphics recently introduced their Capital Harness TVM tool. The software automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models. Capital Harness TVM helps harness manufacturers win business profitably, and is also a platform for other activities such as value engineering and process optimization.