EDA Blog » EDA Tools

Texas Instruments Introduces ULP Advisor Software Code Analysis Tool

Ken Cheung — Tue, 22 May 2012 17:30:48 +0000

Texas Instruments introduced the ULP (Ultra-Low Power) Advisor software code analysis tool. The TI ULP Advisor tool provides a static code analyzer that flags software code and offers ultra-low-power tips and tricks to help developers understand where to improve code, line by line. This results in milliamps and nanoamps saved in designs for ultimate low-power performance. ULP Advisor software is available now. It is included in the latest install of Code Composer Studio IDE version 5.2.

Twitter @edablog : : Free Trade Publications : : Jobs : : EDA Blog : : FPGA Blog : : Embedded Star : : EDA Geek : : Dad Blog
© 2012 Online Destiny Ltd : : EDA Blog is a trademark of Online Destiny Ltd

HiPer Simulation A/MS Features Tools from Tanner EDA, Aldec

Ken Cheung — Mon, 21 May 2012 15:36:13 +0000

Tanner EDA and Aldec teamed together on HiPer Simulation A/MS, which is an integrated co-simulation solution for analog and mixed-signal (A/MS) design. HiPer Simulation A/MS includes Tanner EDA’s T-Spice analog design capture and simulation tool, and Aldec’s Riviera-PRO mixed language digital simulator. The integrated solution helps both analog and digital designers to seamlessly resolve A/MS verification problems from one cohesive, integrated platform. HiPer Simulation A/MS is available on both Windows and Linux.

Carbon Design Systems Launches Performance Analysis Kits

Ken Cheung — Wed, 16 May 2012 16:31:51 +0000

Carbon Design Systems is accelerating the analysis, optimization and verification of system-on-chip (SoC) performance with their new Carbon Performance Analysis Kits (CPAK). The CPAK family for ARM Cortex processors includes reference hardware and software designs along with analysis and debug software for the Cortex-A9, Cortex-A15 and Cortex-A7 cores, and the ARM big.LITTLE subsystem. The CPAK Family for ARM Cortex A-Series Processors will be available in bare metal and Linux configurations in this quarter. Android configurations will be available in the second half of this year.

Cadence Adds In-Circuit Acceleration to System Development Suite, Expands VIP Catalog

Ken Cheung — Tue, 15 May 2012 17:11:15 +0000

Cadence Design Systems made two announcements today. First, the company developed new in-circuit acceleration based on the Incisive and Palladium XP platforms for their System Development Suite. Cadence’s second announcement involved extensions to the Verification IP Catalog for acceleration and emulation that enable engineers to go beyond simulation to speed verification of large-scale SoCs, sub-systems and systems.

STMicroelectronics Introduces STM3220G-JAVA Starter Kit

Ken Cheung — Mon, 14 May 2012 16:12:30 +0000

STMicroelectronics introduced the STM3220G-JAVA Starter Kit. The STM3220G-JAVA kit is a complete platform for evaluating the development of embedded applications in Java for the STM32 F2 series microcontrollers. The new Java tool includes an evaluation version of IS2T’s MicroEJ Software Development Kit (SDK) and the STM32F2 series microcontroller evaluation board providing everything engineers need to start their projects. The STM3220G-JAVA Starter Kit is available now. It is priced at $349.

Sigrity Launches XcitePI IO Interconnect Model Extraction

Ken Cheung — Mon, 14 May 2012 06:59:31 +0000

Sigrity launched their XcitePI IO Interconnect Model Extraction and Assessment software. The tool provides accurate system-level analysis of high-speed channels and buses by generating precise chip IO power/ground and signal interconnect models. XcitePI IO Interconnect Model Extraction is available on Windows and Linux platforms. Prices start at $108,000 for a 3-year license. The new tool is part of Sigrity’s XcitePI chip-level analysis family that supports both pre- and post-layout design improvement.

SynaptiCAD Verilog2VHDL Tool Now Supports Verilog 2005

Ken Cheung — Thu, 03 May 2012 15:18:28 +0000

SynaptiCAD rolled out a new version of their Verilog2VHDL tool. The SynaptiCAD V2V tools translate bidirectionally between Verilog and VHDL source code. The translators are are ideal for converting behavioral and/or RTL-level code to a preferred design language. The V2V translation software is available on Windows and Linux. The SynaptiCAD software can be licensed on either a permanent or leased basis, and both floating and node-locked versions are available.

ANSYS Introduces RedHawk-3DX 20nm Power Sign-off Solution

Ken Cheung — Tue, 01 May 2012 17:23:48 +0000

ANSYS launched RedHawk-3DX, which is a fourth-generation power sign-off solution. RedHawk-3DX is designed to meet the power, performance and price demands of low-power mobile, high-performance computing, consumer and automotive electronics. RedHawk-3DX extends previous generations’ capabilities to address sub-20 nanometer (nm) designs with 3+ gigahertz performance and billions of gates. It is also architected to support the simulation of emerging chip and packaging technologies using multi-die three-dimensional ICs (3D-ICs) for smart electronic products.

Xilinx Vivado Design Suite Supports All Programmable Devices

Ken Cheung — Thu, 26 Apr 2012 15:19:54 +0000

Xilinx introduced their Vivado Design Suite, which is an IP and system-centric design environment for accelerating the design of all programmable devices. The Vivado Design Suite version 2012.1 is available as part of an early access program. Public access will start with version 2012.2 early this summer, followed by WebPACK availability and Zynq-7000 extensible processing platform (EPP) support later in the year. ISE Design Suite Edition customers with current support will be provided the new Vivado Design Suite Editions in addition to ISE at no additional cost.

Mentor Graphics Introduces Questa Functional Verification Platform v10.1

Ken Cheung — Mon, 16 Apr 2012 14:49:28 +0000

Mentor Graphics rolled out version 10.1 of their Questa functional verification platform. The 10.1 release features increased simulation and verification performance, enhanced support of the Universal Verification Methodology (UVM), accelerated coverage closure, and low power verification with comprehensive Unified Power Format (UPF) support. Questa functional verification platform is a tightly integrated solution for the functional verification of complex System-on-Chip (SoC), ASIC and FPGA designs.