ClioSoft, Synopsys, MunEDA, Seminar, Analog Mixed-signal, Design
ClioSoft, Synopsys, and MunEDA are offering a seminar about analog design solution. The seminar will explain how to use advanced design and simulation tools, analog intellectual property (IP), and design data management (DDM) solutions to improve productivity for designers of analog/ mixed signal (A/MS) and custom integrated circuits. The seminar will take on Thursday, March [...]
System Optimization Techniques for Peak SoC Performance Webinar
Sonics and JEDA Technologies have an on-demand webinar for optimizating SoC performance. The webcast, System Optimization Techniques for Peak SoC Performance, is ideal for IC, system, and SoC designers working on next-generation silicon for advanced digital entertainment and mobile devices. The presenters are Ravi Chopra (Application Engineer, Sonics) and Andrea Kroll (VP of Marketing and [...]
Unicoi Systems Fusion SIP 5.1
Unicoi Systems (Unicoi) introduced version 5.1 Fusion SIP tool for embedded systems developers. The latest version of the tool offers support for secure VoIP telephony and intercommunications equipment. Fusion SIP v5.1 provides updated support for NAT Traversal (RFC 3581) and Session Timers (RFC 4028).
PragmaDev Real Time Developer Studio v4.1
PragmaDev introduced Real Time Developer Studio (RTDS) V4.1. The latest version of Real Time Developer Studio offers over 40 new features. RTDS is a complete model driven development tool for real time and embedded systems based on international standards. Real Time Developer Studio offers three levels of modeling: informal, semi-formal, and fully formal. While informal [...]
Geensoft AUTOSAR Re-targeting Tool for AUTOSAR Builder Tool Suite
Geensoft introduced the AUTOSAR Re-targeting Tool (ART) module for the AUTOSAR Builder tool suite for the development of AUTOSAR-compliant automotive embedded systems. The ART module offers automatic generation of AUTOSAR-compliant C code that is ready to be embedded on target ECUs, from both new and legacy MATLAB/Simulink models using RTW.
Tekton Static Timing Analysis Platform
Magma Design Automation launched Tekton timing analysis platform. The Tekton platform includes QCP, which is a fast, high-capacity, full-chip extractor that delivers results with the accuracy of the industry standard, QuickCap. Tekton and QCP are in limited release. According to Magma, Tekton is the only STA solution that meets the multi-scenario analysis problems of today [...]
Synopsys Galaxy Custom Designer with SmartDRD Technology
Synopsys Galaxy Custom Designer now features SmartDRD design-rules-driven technology. SmartDRD technology enables layout engineers to more quickly achieve design-rule-check (DRC) clean designs with significantly reduced effort for analog and custom designs. SmartDRD automates many DRC repair tasks. Until now, custom layout has been primarily handled using manual methods. With SmartDRD technology, layout engineers can identify [...]
Geensoft Reqtify 2010 Tool Suite
Geensoft introduced Reqtify 2010 tool suite for the automated management of embedded hardware and software requirements capture, traceability and impact analysis throughout the entire development lifecycle. Reqtify 2010 offers improved productivity through an extensive range of new and enhanced plug-in tools, features and interfaces. Reqtify has been deployed or qualified for application development under certification [...]
Synopsys System Studio with Matrix and Vector Data-Type Support
Synopsys introduced new capabilities for their System Studio C/C++ model-based analysis and simulation environment. System Studio now supports matrix and vector data-type, which reduces the coding and debugging effort necessary to author signal processing simulation models. In addition, System Studio integrates highly efficient parallelized matrix and vector function libraries optimized for multicore systems. The function [...]
Forte Design Systems Releases CellMath Designer and IP Software
Forte Design Systems released the latest version of CellMath Designer datapath synthesis and Cellmath IP software. The CellMath family enables register transfer level (RTL) designers to reduce area, improve performance and lower power consumption for their existing datapath-intensive design blocks. U.S. pricing starts at $120,000 for a one-year, time-based license.
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