Cadence Tempus Timing Signoff Solution Speeds Timing Closure
Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.
Synopsys IC Compiler 2013.03 Speeds Design Closure
Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.
Mentor Graphics Introduces Capital Harness TVM Tool
Mentor Graphics recently introduced their Capital Harness TVM tool. The software automatically generates detailed harness manufacturing process and cost data that is specific to each harness design, each factory and each company’s cost models. Capital Harness TVM helps harness manufacturers win business profitably, and is also a platform for other activities such as value engineering [...]
Data Translation Introduces QuickDAQ 2013 for Data Acquisition
Data Translation introduced QuickDAQ 2013. The new software application supports all of Data Translation data acquisition modules. QuickDAQ 2013 has been designed to accommodate a wide variety of sensor types and various throughput speeds for our many OEM’s and end-users. Engineers can use one application software package for many measurement needs with no software changes. [...]
Cadence Design Systems Debuts Incisive Enterprise Simulator v13.1
Cadence Design Systems released version 13.1 of the Incisive Enterprise Simulator. The latest release of the software tool improves low-power verification productivity of complex SoCs by 30%. Cadence Incisive Enterprise Simulator v13.1 features new capabilities that ease the challenge of verifying all of today’s power-aware designs.
Download ADLINK AD-Logger and DAQBench for Free
Thanks to ADLINK Technology, engineers can download AD-Logger and DAQBench for free. AD-Logger is a ready-to-run data capture application. DAQBench provides ActiveX controls used for creating professional instrumentation applications using ActiveX development environments. AD-Logger and DAQBench are compatible with ADLINK’s full range of data acquisition modules and digitizers. Both tools are compatible with 32-bit Windows [...]
Synopsys Debuts Virtualizer Development Kit for Freescale Qorivva Microcontroller
Synopsys introduced the Virtualizer Development Kit (VDK) for Freescale Semiconductor’s Qorivva microcontroller family. The Synopsys VDK accelerates the development of automotive control applications in powertrain/hybrid, chassis/safety and body electronic control units (ECUs). Synopsys’ automotive VDKs help OEMs and tier-one suppliers to enhance their embedded software development processes by starting earlier, improving productivity and enabling more [...]
Synopsys Embedded Vision Development System Reduces Bring-up Time by Months
Synopsys introduced the Embedded Vision Development System. The new Synopsys is an integrated solution for the acceleration of the design of processors for embedded vision. It is based on Synopsys’ Processor Designer tool set and Synopsys’ HAPS FPGA-based prototyping system. The Embedded Vision Development System is immediately available now.
Kontron Unveils SMARC Starterkit for Embedded ARM Processors
Kontron introduced the SMARC Starterkit. The ready-to-use kit enables developers to get started with embedded ARM processors. The Kontron SMARC Starterkit includes a sturdy transport case, has all the cables already connected and is equipped with all the necessary components, including a display and power supply. All documentation is provided on a USB drive. The [...]
Mentor Graphics Launches iSolve SAS and Verification IP Solutions
Mentor Graphics introduced iSolve SAS and SAS transaction-based verification IP (VIP) solution. iSolve SAS is a plug-and-play hardware interface to the Veloce family of hardware emulators. The VIP solution delivers both a simulation environment, using the Questa verification platform, and accelerated simulation environment using the Veloce hardware for the verification of SAS Gen2-compliant devices. Both [...]
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