Category Archives: DSPs

digital signal processors, dsp

Tensilica ConnX BBE16 BaseBand Engine DSP

The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. It is a click-box configuration option with the configurable Xtensa LX3 processor core. Designers can also choose from a number of other configuration options (memories, interfaces, etc.) when designing their core. The ConnX BBE16 and an evaluation kit will be available in the second quarter of 2010.

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Tensilica HiFi EP Audio DSP IP Core

Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. The enhancements result in up to 40% lower power and up to a 50 percent size reduction.

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CEVA Application Optimizer for C-based Development of DSP Cores

CEVA launched the Application Optimizer, which is an integrated optimizing toolchain that enables an end-to-end, fully C-based development flow for licensable DSP cores. Available as part of the CEVA-Toolbox Software Development Environment, the Application Optimizer enables application developers to easily develop software for CEVA’s DSPs purely in C-Level, eliminating any hand-written assembly coding. This results in significantly better overall performance and a shorter design cycle for SoC designs.

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Microchip PIC32 DSP Library

Microchip Technology introduced their no-cost, royalty-free high performance PIC32 DSP Library. The new library can execute a 256-point, 16-bit RADIX-2 Fast Fourier Transform (FFT) in 283 microseconds. The free evaluation version of the MPLAB C Compiler for PIC32 MCUs, with the new PIC32 DSP Library, can be downloaded. The full version of the C Complier can be purchased for $895.

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Digital Radio Mondiale Decoder on HiFi 2 Audio DSP

Tensilica is offering the Digital Radio Mondiale (DRM) decoder for their HiFi 2 Audio DSP. The implementation is based on software developed by Dolby and has passed Dolby’s certification procedure. As a result, Tensilica’s HiFi 2 Audio DSP core can be used to run all decoders required throughout the world for digital radio. Tensilica’s HiFi 2 Audio DSP also supports four other terrestrial and satellite standards: DAB, DAB+, HD Radio, and XM Radio. The DRM decoder is available now.

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CEVA-HD-Audio DSP Solution

CEVA, Inc. (Nasdaq: CEVA) (LSE: CVA) introduced the CEVA-HD-Audio single-core solution for HD audio applications. The CEVA-HD-Audio configurable and programmable platform is ideal for home entertainment and consumer products — including Blu-ray DVDs, DTVs, set-top boxes and other home A/V devices. The CEVA-HD-Audio solution is currently available for licensing.

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Ambarella A5 Hybrid Camera Platform

Ambarella, Inc. introduced the A5 system-on-a-chip (SoC) platform for hybrid cameras. The A5 platform features 10 mega-pixel (MP) still images, full high-definition (HD) recording, and simultaneous dual-resolution recording for fast internet sharing. The A5 SoC platform enables consumers to take high-quality photos and video in affordably priced pocket-sized cameras. Consumer hybrid cameras based on the A5 platform is expected to be priced under $199. The A5 platform is available now in sampling quantities. Manufacturers can choose multiple configurations to accommodate their specific requirements. Evaluation kits are also available now.
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Digital Signal Processing Theory Architecture and Algorithms Course

The Institute for System Level Integration and Steepest Ascent Ltd. will host a digital signal processing course at the Bath Innovation Centre on October 20-23, 2008. The 4-day intensive course will focus on digital signal processing, architectures, and algorithms. The event will provide attendees with a solid and intuitive understanding of the essential digital signal processing tools — such as digital filters, FFTs, correlators, adaptive systems, and multirate systems. The underlying theory, algorithms, and practical knowledge is then applied across a range of DSP applications including QAM/QPSK digital communications, time-frequency signal analysis, adaptive data equalisation, acoustic echo cancellers, multirate systems, and sigma delta coding.

The course comes at a time when DSP is increasingly being applied to more powerful general purpose microprocessors, field-programmable gate arrays, digital signal controllers and stream processors. It is suitable for all engineering, marketing and technical management staff. By delivering a sound grounding in DSP theory and practice, participants will leave with the knowledge required to apply DSL solutions to problems within their given domains.

More info: Institute for System Level Integration

BDTI Benchmarks for picoChip PC102 multicore-DSP

According to Berkeley Design Technology (BDTI) benchmarks, picoChip’s PC102 multicore signal processing device has a 40-fold advantage in price-performance over traditional DSP processors solutions in key communications benchmarks, and 8-times higher absolute performance.

The BDTI Communications Benchmark (OFDM)(TM) shows that the PC102 picoArray(TM) can implement 14 benchmark channels in a single device running 160MHz. This represents a cost per channel of $6.78, some 40 times less than the figure for competing traditional DSPs.

The BDTI Communication Benchmark (OFDM) is designed to be representative of the signal processing workloads found in communications equipment for applications such as DSL, cable modems and wireless systems. It is intended to enable benchmarking and comparison of a wide range of devices on real-world, datapath-focused applications. Each channel of the benchmark is a representative model of an Orthogonal Frequency Division Multiplex (OFDM) modem, including filter, Fast Fourier Transform (FFT), slicer and Viterbi decoder.

Certified Results for the BDTI Communications Benchmark (OFDM)[TM]

High Capacity Results
TI TMS320C6455 1GHz 1.09 channels $268.50/channel (without use of Viterbi coprocessor)
TI TMS320C6455 1GHz <1.8 channels >$163/channel (estimated, with use of Viterbi coprocessor)
Freescale MSC8144 3.5 channels $57/channel (estimated)
Altera 1S80-6 60 channels $10/channel (previous generation)
picoChip PC102 @ 160MHz 14 channels $6.78/channel (previous generation, 130nm)
Xilinx Virtex-4 FX140– 10 speed grade 432 channels $2.97/channel

TI TMS320C6410 400MHz 0.31 channels $48.23/channel
Freescale MSC8144 3.5 channels $66/channel (estimated)
Altera 1S80-6 60 channels $10/channel (previous generation)
picoChip PC102 14 channels $6.78/channel (previous generation, 130nm)
Xilinx Virtex-4 SX25 Slowest speed grade 64 channels $1.39/channel
Altera Stratix II 2S15 Slowest speed grade 20 channels $2.75/channel

More info:
picoChip multicore-DSP 40x Better in BDTI Benchmarks

DSPedia Technical Course

hueggenberg is offering a technical course on theory, algorithms, and architectures of digital signal processing. The course will take place from November 6th to 9th, 2007 in Munich. The four day course will be conducted in English and covers the basics of signal processing and the generic DSP system via frequency domain analysis, digital filtering, DSP software/hardware, DSP audio/baseband processing, signal (audio) source coding, adaptive DSP algorithms, computationally efficient DSP linear systems, digital communications, DSP for mobile and wireless, DSP (software) enabled radio architectures, and DSP on FPGAs.

The complex mathematical theory associated with digital signal processing is presented in an intuitive and straightforward style. The course is aimed at a wide audience reaching from scientists, engineers, project managers to even marketing staff. The following prior experience is useful but not essential: programming principles, electrical engineering principles, Bachelor level mathematics.

The training will feature presentations and design sessions. Special attention is paid to practical experience; each presentation is concluded by a hands-on session in which attendees will be able to simulate and implement the structures and architectures introduced. Each attendee will receive a comprehensive set of notes and examples for in depth study after the course.

More information: hueggenberg DSPedia Technical Course »