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	<title>EDA Blog &#187; DSPs</title>
	<atom:link href="http://edablog.com/category/dsp/feed/" rel="self" type="application/rss+xml" />
	<link>http://edablog.com</link>
	<description>Electronic Design Automation Software, Hardware, and Components</description>
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		<title>Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core</title>
		<link>http://edablog.com/2012/02/29/bbe32ue-baseband-soc/</link>
		<comments>http://edablog.com/2012/02/29/bbe32ue-baseband-soc/#comments</comments>
		<pubDate>Wed, 29 Feb 2012 18:16:24 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[ConnX BBE32UE]]></category>
		<category><![CDATA[IP core]]></category>
		<category><![CDATA[LTE-Advanced]]></category>
		<category><![CDATA[PHY]]></category>
		<category><![CDATA[programmable]]></category>
		<category><![CDATA[SoC]]></category>
		<category><![CDATA[system-on-chip]]></category>
		<category><![CDATA[Tensilica]]></category>
		<category><![CDATA[User Equipment]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7697</guid>
		<description><![CDATA[Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW [...]]]></description>
			<content:encoded><![CDATA[<p>Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW (28 nm HPL process). The ConnX BBE32UE is available now for early access customers. General product release is planned for the third quarter of 2012.</p>
<p><p>Read more: <a href="http://edablog.com/2012/02/29/bbe32ue-baseband-soc/">Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/02/29/bbe32ue-baseband-soc/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/02/29/bbe32ue-baseband-soc/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core</title>
		<link>http://edablog.com/2012/01/10/hifi-3-dsp/</link>
		<comments>http://edablog.com/2012/01/10/hifi-3-dsp/#comments</comments>
		<pubDate>Tue, 10 Jan 2012 17:51:04 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[audio]]></category>
		<category><![CDATA[digital signal processor]]></category>
		<category><![CDATA[HiFi 3]]></category>
		<category><![CDATA[IP core]]></category>
		<category><![CDATA[Tensilica]]></category>
		<category><![CDATA[Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core]]></category>
		<category><![CDATA[Voice]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=7525</guid>
		<description><![CDATA[Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there&#8217;s a performance improvement [...]]]></description>
			<content:encoded><![CDATA[<p>Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there&#8217;s a performance improvement of over 150% for most voice codecs compared to HiFi EP. The HiFi 3 has been delivered to lead customers. General availability will be in March.</p>
<p><p>Read more: <a href="http://edablog.com/2012/01/10/hifi-3-dsp/">Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2012/01/10/hifi-3-dsp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2012/01/10/hifi-3-dsp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2012 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>TI TMDX5502EZDSP and TMDX5509EZDSP eZdsp Development Tools</title>
		<link>http://edablog.com/2011/04/14/c5502-c5509a-dsp/</link>
		<comments>http://edablog.com/2011/04/14/c5502-c5509a-dsp/#comments</comments>
		<pubDate>Thu, 14 Apr 2011 14:02:01 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[Boards, Busses]]></category>
		<category><![CDATA[DSPs]]></category>
		<category><![CDATA[EDA Tools]]></category>
		<category><![CDATA[C5502]]></category>
		<category><![CDATA[C5509A]]></category>
		<category><![CDATA[development tools]]></category>
		<category><![CDATA[Digital Signal Processors]]></category>
		<category><![CDATA[eZdsp]]></category>
		<category><![CDATA[Texas Instruments]]></category>
		<category><![CDATA[TI]]></category>
		<category><![CDATA[TMDX5502EZDSP]]></category>
		<category><![CDATA[TMDX5509EZDSP]]></category>
		<category><![CDATA[TMS320C5000]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=6697</guid>
		<description><![CDATA[Texas Instruments introduced the TMDX5502EZDSP and TMDX5509EZDSP development tools for C5502 and C5509A digital signal processors. The TI eZdsp development tools are credit card sized and do not require cables. The C5502 eZdsp development tool features a range of integrated peripheral devices, an XDS100v2 emulator, a complete version of CCS IDE v4 and access to [...]]]></description>
			<content:encoded><![CDATA[<p>Texas Instruments introduced the TMDX5502EZDSP and TMDX5509EZDSP development tools for C5502 and C5509A digital signal processors. The TI eZdsp development tools are credit card sized and do not require cables. The C5502 eZdsp development tool features a range of integrated peripheral devices, an XDS100v2 emulator, a complete version of CCS IDE v4 and access to chip support, optimized DSP, image and telecom library with source code. In addition to the features of the C5502 tool, the C5509A eZdsp development tool also includes a USB1.1 slave port and a microSD card slot. The TMDX5502EZDSP is available now for $89 (USD) and the TMDX5509EZDSP is priced at $99 and is also available now.</p>
<p><p>Read more: <a href="http://edablog.com/2011/04/14/c5502-c5509a-dsp/">TI TMDX5502EZDSP and TMDX5509EZDSP eZdsp Development Tools</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2011/04/14/c5502-c5509a-dsp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2011/04/14/c5502-c5509a-dsp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2011 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>IntegrIT Nature DSP Signal+ for Tensilica HiFi Audio DSP</title>
		<link>http://edablog.com/2010/12/16/math-library/</link>
		<comments>http://edablog.com/2010/12/16/math-library/#comments</comments>
		<pubDate>Thu, 16 Dec 2010 19:29:57 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[audio]]></category>
		<category><![CDATA[HiFi]]></category>
		<category><![CDATA[IntegrIT]]></category>
		<category><![CDATA[Math Library]]></category>
		<category><![CDATA[Nature DSP Signal+]]></category>
		<category><![CDATA[Tensilica]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=6281</guid>
		<description><![CDATA[The IntegrIT NatureDSP Math library is now available for Tensilica&#8217;s HiFi Audio DSPs for system-on-chip (SOC) design. The NatureDSP Math library simplifies the software development process for design teams that want to port software codecs to the Tensilica HiFi Audio DSP. The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for [...]]]></description>
			<content:encoded><![CDATA[<p>The IntegrIT NatureDSP Math library is now available for Tensilica&#8217;s HiFi Audio DSPs for system-on-chip (SOC) design. The NatureDSP Math library simplifies the software development process for design teams that want to port software codecs to the Tensilica HiFi Audio DSP. The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for implementation of typical digital signal processing functions which efficiently utilize the HiFi Audio DSP architecture. It contains highly optimized routines for filtering, FFT, matrix, trigonometric and other math operations.</p>
<p><p>Read more: <a href="http://edablog.com/2010/12/16/math-library/">IntegrIT Nature DSP Signal+ for Tensilica HiFi Audio DSP</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/12/16/math-library/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/12/16/math-library/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		</item>
		<item>
		<title>GE Intelligent Platforms AXISLib-GPU Math and DSP Library</title>
		<link>http://edablog.com/2010/09/21/gpgpu-dsp/</link>
		<comments>http://edablog.com/2010/09/21/gpgpu-dsp/#comments</comments>
		<pubDate>Tue, 21 Sep 2010 11:21:28 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[AXISLib-GPU]]></category>
		<category><![CDATA[CUDA]]></category>
		<category><![CDATA[digital signal processing]]></category>
		<category><![CDATA[GE Intelligent Platforms]]></category>
		<category><![CDATA[GPGPU]]></category>
		<category><![CDATA[math]]></category>
		<category><![CDATA[NVIDIA]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=5960</guid>
		<description><![CDATA[GE Intelligent Platforms introduced AXISLib-GPU, which is a library of optimized math and DSP functions that supports the rapid development of multiprocessing applications that take advantage of the power of GPGPU (general purpose processing on a graphics processing unit) technology. AXISLib-GPU supports the development and speeds the deployment of high performance DSP and multiprocessing applications [...]]]></description>
			<content:encoded><![CDATA[<p>GE Intelligent Platforms introduced AXISLib-GPU, which is a library of optimized math and DSP functions that supports the rapid development of multiprocessing applications that take advantage of the power of GPGPU (general purpose processing on a graphics processing unit) technology. AXISLib-GPU supports the development and speeds the deployment of high performance DSP and multiprocessing applications on GE&#8217;s NVIDIA CUDA-enabled GPGPU platforms (such as the IPN250, NPN240 and GRA111). AXISLib-GPU can operate in a standalone mode or as an integral software module within the AXIS Advanced Multiprocessor Integrated Software environment.</p>
<p><p>Read more: <a href="http://edablog.com/2010/09/21/gpgpu-dsp/">GE Intelligent Platforms AXISLib-GPU Math and DSP Library</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/09/21/gpgpu-dsp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/09/21/gpgpu-dsp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Tensilica FLAC Decoder for the Xtensa HiFi Audio DSP</title>
		<link>http://edablog.com/2010/06/30/lossless-codec/</link>
		<comments>http://edablog.com/2010/06/30/lossless-codec/#comments</comments>
		<pubDate>Wed, 30 Jun 2010 17:28:37 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[Codec]]></category>
		<category><![CDATA[Decoder]]></category>
		<category><![CDATA[FLAC]]></category>
		<category><![CDATA[Free Lossless Audio Codec]]></category>
		<category><![CDATA[HiFi Audio]]></category>
		<category><![CDATA[IP core]]></category>
		<category><![CDATA[Tensilica]]></category>
		<category><![CDATA[Xtensa]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=5665</guid>
		<description><![CDATA[Tensilica&#8217;s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not [...]]]></description>
			<content:encoded><![CDATA[<p>Tensilica&#8217;s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not encumbered by patents, and has an open-source reference implementation. Tensilica&#8217;s FLAC decoder supports both stereo and multi-channel formats.</p>
<p><p>Read more: <a href="http://edablog.com/2010/06/30/lossless-codec/">Tensilica FLAC Decoder for the Xtensa HiFi Audio DSP</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/06/30/lossless-codec/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/06/30/lossless-codec/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>VSIDE Integrated Development Environment for VSDSP DSP Family</title>
		<link>http://edablog.com/2010/05/13/vlsi-solution-ide/</link>
		<comments>http://edablog.com/2010/05/13/vlsi-solution-ide/#comments</comments>
		<pubDate>Thu, 13 May 2010 16:19:43 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IDE]]></category>
		<category><![CDATA[Development]]></category>
		<category><![CDATA[Digital Signal Processors]]></category>
		<category><![CDATA[VLSI Solution]]></category>
		<category><![CDATA[VSDSP]]></category>
		<category><![CDATA[VSIDE]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=5417</guid>
		<description><![CDATA[VLSI Solution introduced the VSIDE integrated development environment for the V16/40-bit VSDSP digital signal processor family. VSIDE offers a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, and profiler. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform. Read more: VSIDE [...]]]></description>
			<content:encoded><![CDATA[<p>VLSI Solution introduced the VSIDE integrated development environment for the V16/40-bit VSDSP digital signal processor family. VSIDE offers a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, and profiler. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform.</p>
<p><p>Read more: <a href="http://edablog.com/2010/05/13/vlsi-solution-ide/">VSIDE Integrated Development Environment for VSDSP DSP Family</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/05/13/vlsi-solution-ide/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/05/13/vlsi-solution-ide/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<item>
		<title>Tensilica ConnX 545CK 8-MAC VLIW Digital Signal Processor Core</title>
		<link>http://edablog.com/2010/04/22/connx-545ck-dsp/</link>
		<comments>http://edablog.com/2010/04/22/connx-545ck-dsp/#comments</comments>
		<pubDate>Thu, 22 Apr 2010 17:31:32 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[8-MAC]]></category>
		<category><![CDATA[ConnX 545CK]]></category>
		<category><![CDATA[Core]]></category>
		<category><![CDATA[digital signal processor]]></category>
		<category><![CDATA[multiply-accumulate]]></category>
		<category><![CDATA[Tensilica]]></category>
		<category><![CDATA[VLIW]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=5293</guid>
		<description><![CDATA[Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die [...]]]></description>
			<content:encoded><![CDATA[<p>Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die and up to 30% lower power consumption. The ConnX 545CK Revision C is available now.</p>
<p><p>Read more: <a href="http://edablog.com/2010/04/22/connx-545ck-dsp/">Tensilica ConnX 545CK 8-MAC VLIW Digital Signal Processor Core</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/04/22/connx-545ck-dsp/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/04/22/connx-545ck-dsp/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>Tensilica ConnX BBE16 BaseBand Engine DSP</title>
		<link>http://edablog.com/2010/02/08/lte-4g-soc/</link>
		<comments>http://edablog.com/2010/02/08/lte-4g-soc/#comments</comments>
		<pubDate>Mon, 08 Feb 2010 17:49:58 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[4G]]></category>
		<category><![CDATA[Base Stations]]></category>
		<category><![CDATA[BaseBand Engine]]></category>
		<category><![CDATA[ConnX BBE16]]></category>
		<category><![CDATA[Handsets]]></category>
		<category><![CDATA[LTE]]></category>
		<category><![CDATA[Tensilica]]></category>
		<category><![CDATA[Wireless]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=4745</guid>
		<description><![CDATA[The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. [...]]]></description>
			<content:encoded><![CDATA[<p>The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. It is a click-box configuration option with the configurable Xtensa LX3 processor core. Designers can also choose from a number of other configuration options (memories, interfaces, etc.) when designing their core. The ConnX BBE16 and an evaluation kit will be available in the second quarter of 2010.</p>
<p><p>Read more: <a href="http://edablog.com/2010/02/08/lte-4g-soc/">Tensilica ConnX BBE16 BaseBand Engine DSP</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/02/08/lte-4g-soc/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/02/08/lte-4g-soc/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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		<title>Tensilica HiFi EP Audio DSP IP Core</title>
		<link>http://edablog.com/2010/02/01/hifi-2-blu-ray/</link>
		<comments>http://edablog.com/2010/02/01/hifi-2-blu-ray/#comments</comments>
		<pubDate>Mon, 01 Feb 2010 19:47:41 +0000</pubDate>
		<dc:creator>Ken Cheung</dc:creator>
				<category><![CDATA[DSPs]]></category>
		<category><![CDATA[IP Cores]]></category>
		<category><![CDATA[audio]]></category>
		<category><![CDATA[Core]]></category>
		<category><![CDATA[Designs]]></category>
		<category><![CDATA[digital signal processing]]></category>
		<category><![CDATA[HiFi 2]]></category>
		<category><![CDATA[HiFi EP]]></category>
		<category><![CDATA[IP]]></category>
		<category><![CDATA[Smartphone]]></category>
		<category><![CDATA[SoC]]></category>
		<category><![CDATA[system-on-chip]]></category>
		<category><![CDATA[Tensilica]]></category>

		<guid isPermaLink="false">http://edablog.com/?p=4672</guid>
		<description><![CDATA[Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. [...]]]></description>
			<content:encoded><![CDATA[<p>Tensilica launched HiFi EP, which is a superset of the HiFi 2 architecture that is optimized for simultaneous multichannel codec support and/or continuously expanding audio pre- and post-processing in home entertainment products such as Blu-ray Disc players, digital television (DTV), and Smartphones. HiFi EP has also been enhanced for efficient, high-quality voice pre- and post-processing. The enhancements result in up to 40% lower power and up to a 50 percent size reduction.</p>
<p><p>Read more: <a href="http://edablog.com/2010/02/01/hifi-2-blu-ray/">Tensilica HiFi EP Audio DSP IP Core</a></p><p align="center"><a href="http://api.tweetmeme.com/share?url=http://edablog.com/2010/02/01/hifi-2-blu-ray/"><img src="http://api.tweetmeme.com/imagebutton.gif?url=http://edablog.com/2010/02/01/hifi-2-blu-ray/" height="61" width="51" /></a></p>
<p align="center"><a href="http://twitter.com/edablog">Twitter @edablog</a> : : <a href="http://embeddedstar.tradepub.com/">Free Trade Publications</a> : : <a href="http://www.embeddedstar.com/careers/">Jobs</a> : : <a href="http://edablog.com/">EDA Blog</a> : : <a href="http://fpgablog.com/">FPGA Blog</a> : : <a href="http://www.embeddedstar.com/">Embedded Star</a> : : <a href="http://edageek.com/">EDA Geek</a> : : <a href="http://daddyforever.com/">Dad Blog</a><br />© 2010 <a href="http://www.onlinedestiny.com/">Online Destiny Ltd</a> : : EDA Blog is a trademark of Online Destiny Ltd</p>]]></content:encoded>
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