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'DSPs' Category Archive

Tensilica Debuts HiFi Mini Digital Signal Processor IP Core

Posted by Ken Cheung in DSPs,IP Cores on Monday, January 7, 2013

Tensilica announced their HiFi Mini DSP IP core. According to the company, the digital signal processor core is the smallest, lowest power DSP IP core supporting always listening voice trigger and speech command modes. The HiFi Mini DSP IP core will be available in March 2013. The core is ideal for smartphones, tablets, appliances, and [...]

Tensilica Unveils ConnX BBE32UE Digital Signal Processor IP Core

Posted by Ken Cheung in DSPs,IP Cores on Wednesday, February 29, 2012

Tensilica introduced their ConnX BBE32UE digital signal processor IP core. The ConnX BBE32UE DSP core is ideal for baseband SOC (system-on-chip) designs. Coupled with Tensilica Baseband Dataplane processors (DPUs), the new core can help engineers realize a fully software programmable, flexible modem for LTE-Advanced user equipment category 7 PHY (Layer 1) in less than 200mW [...]

Tensilica HiFi 3 Audio/Voice Digital Signal Processor IP Core

Posted by Ken Cheung in DSPs,IP Cores on Tuesday, January 10, 2012

Tensilica introduced the HiFi 3 audio/voice digital signal processor intellectual property core for system-on-chip design. HiFi 3 DSP has an 80% increase in performance for the FFT (fast Fourier transform), FIR (finite impulse response), and IIR (infinite impulse response) math functions that are essential in audio pre- and post-processing. In addition, there’s a performance improvement [...]

TI TMDX5502EZDSP and TMDX5509EZDSP eZdsp Development Tools

Posted by Ken Cheung in Boards, Busses,DSPs,EDA Tools on Thursday, April 14, 2011

Texas Instruments introduced the TMDX5502EZDSP and TMDX5509EZDSP development tools for C5502 and C5509A digital signal processors. The TI eZdsp development tools are credit card sized and do not require cables. The C5502 eZdsp development tool features a range of integrated peripheral devices, an XDS100v2 emulator, a complete version of CCS IDE v4 and access to [...]

IntegrIT Nature DSP Signal+ for Tensilica HiFi Audio DSP

Posted by Ken Cheung in DSPs on Thursday, December 16, 2010

The IntegrIT NatureDSP Math library is now available for Tensilica’s HiFi Audio DSPs for system-on-chip (SOC) design. The NatureDSP Math library simplifies the software development process for design teams that want to port software codecs to the Tensilica HiFi Audio DSP. The IntegrIT Nature DSP Signal+ is a collection of signal processing routines needed for [...]

GE Intelligent Platforms AXISLib-GPU Math and DSP Library

Posted by Ken Cheung in DSPs on Tuesday, September 21, 2010

GE Intelligent Platforms introduced AXISLib-GPU, which is a library of optimized math and DSP functions that supports the rapid development of multiprocessing applications that take advantage of the power of GPGPU (general purpose processing on a graphics processing unit) technology. AXISLib-GPU supports the development and speeds the deployment of high performance DSP and multiprocessing applications [...]

Tensilica FLAC Decoder for the Xtensa HiFi Audio DSP

Posted by Ken Cheung in DSPs,IP Cores on Wednesday, June 30, 2010

Tensilica’s HiFi Audio DSP family of IP (intellectual property) cores for SOC (system-on-chip) design now features the Free Lossless Audio Codec (FLAC) decoder. FLAC is an audio format similar to MP3, but lossless so the audio is compressed without any loss in quality. It is not a proprietary format. As a result, FLAC is not [...]

VSIDE Integrated Development Environment for VSDSP DSP Family

Posted by Ken Cheung in DSPs,IDE on Thursday, May 13, 2010

VLSI Solution introduced the VSIDE integrated development environment for the V16/40-bit VSDSP digital signal processor family. VSIDE offers a complete set of development utilities, including an optimizing ANSI-C compiler, assembler, linker, and profiler. All programs are integrated into a simple-to-use, easy-to-learn package running on a PC / Windows XP or Vista platform.

Tensilica ConnX 545CK 8-MAC VLIW Digital Signal Processor Core

Posted by Ken Cheung in DSPs,IP Cores on Thursday, April 22, 2010

Tensilica announced Revision C of the ConnX 545CK 8-MAC (multiply-accumulate) VLIW (very long instruction word) DSP (digital signal processor) core for system-on-chip (SOC) designs. In 65GP optimized for high speed, the ConnX 545CK delivers over 600 MHz operation. The third generation dataplane processor (DPU) core deliver up to 20% faster clock speed, 11% smaller die [...]

Tensilica ConnX BBE16 BaseBand Engine DSP

Posted by Ken Cheung in DSPs,IP Cores on Monday, February 8, 2010

The ConnX BBE16, from Tensilica, is a second generation baseband engine for LTE (long-term evolution) and 4G baseband SOC (system-on-chip) designs. The ConnX BBE16 is an ultra-high performance 16-MAC fixed-point DSP engine. It is based on an 8-way SIMD (Single Instruction, Multiple Data), 3-issue VLIW (Very Long Instruction Word) architecture with two 128-bit load/store units. [...]

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