Synopsys introduced their new DesignWare ARC EM SEP (Safety Enhancement Package) Processor core for automotive safety-compliant applications. The ARC EM SEP core is configurable to meet the performance, power and area requirements of each target application. Giving designers the ability to define custom instructions facilitates the integration of proprietary hardware accelerators that improve application-specific performance while reducing power consumption and the amount of memory required — critical requirements in embedded automotive designs.
Synopsys DesignWare ARC EM SEP Processor Core Features
- Integrated ASIL D hardware features including error-correcting code (ECC), parity support, user-programmable watchdog timer and dual-core lockstep interface
- MetaWare Compiler certified ASIL D ready
- Extensive safety documentation to ease the ISO 26262 certification process
- Target applications include embedded automotive applications requiring ISO 26262 safety compliance such as movement and acceleration sensors, electric power steering and advanced driver assistance systems (ADAS)
The 32-bit ARC EM SEP processor is based on the highly efficient ARC EM4 core. It delivers performance up to 300 MHz and power consumption as low as 16 µW/MHz on typical 65-nanometer (nm) low power silicon processes, with integrated hardware safety features that enable ASIL D compliance in support of the ISO 26262 standard.
In addition, the DesignWare ARC MetaWare Compiler helps software developers accelerate the development of ISO 26262-compliant code and is undergoing ASIL D readiness certification by SGS-TUV Saar, a leading independent safety certification company. The combination of a safety-enhanced processor and compiler makes the ARC EM SEP core ideally suited for system-on-chips (SoCs) designed for embedded automotive applications such as movement and acceleration sensors, advanced driver assistance systems and electric power steering.
The EM SEP processor integrates hardware safety features including ECC for single-bit error correction and double-bit error detection, and parity protection for single-bit error detection on closely coupled memories. To minimize system-level latencies and silicon area, SoC peripherals can be directly mapped to the CPU to enable single cycle access. Native ARM AMBA, AHB, AHB-Lite and BVCI standard interfaces are configurable for 32-bit or 64-bit transactions to optimize system throughput. Support for ARC EM SEP in Synopsys’ Virtualizer virtual prototyping environment allows for seamless integration with tools such as Mathworks’ Simulink, Vector’s CANoe and Synopsys’ Saber to enable virtual hardware-in-the-loop (HIL) simulation and fault testing.
The DesignWare ARC MetaWare Compiler and accompanying safety documentation help developers of safety-critical systems fulfill the requirements of the ISO 26262 standard. The IP safety collateral, including a safety manual and safety guide, makes it easier for automotive designers to prepare their documentation for ISO 26262 compliance testing. The compiler is part of the ARC MetaWare Development Toolkit, a complete solution for developing, debugging and optimizing embedded software targeted for ARC processors.
More info: Synopsys DesignWare ARC EM SEP Processor