Cadence Design Systems Introduces 28nm Data Convertor IP

Cadence 28nm Data Convertor IP family

Cadence Design Systems announced a suite of ultra-fast, low-power analog intellectual property (IP) products. The new data converter family includes 7-bit 3GSPS dual ADC and DAC, 11-bit 1.5GSPS dual ADC, and 12-bit 2GSPS dual DAC. The converters are ideal for designers working with emerging high-speed protocols such as WiGig (802.11ad), which runs on a 60 GHz spectrum with potential data throughput up to 7Gbps, as well as LTE and LTE Advanced. The Cadence 28nm Data Convertor IP family is available now.

The ADC IP cores are developed with a parallel Successive Approximation Array (SAR) architecture, producing extremely fast and scalable sample rates. High Effective-Number-of-Bits (ENOB) values are achieved with a unique implementation and built-in background auto calibration, producing more accurate conversion and consistent performance. The Cadence IP includes features such as differential data inputs, reference and timing generator, internal offset correction, and voltage regulators for improved supply noise immunity.

The DAC IP cores use a current switching architecture and include a digital multiplexer and FIFO for easy integration into an SoC. The DACs include digital gain control and all required reference circuitry.

All the IP includes multi-level power-down modes for additional power savings, a built-in analog test bus for design testability, and single-ended CMOS or differential Current-Mode Logic (CML) clock inputs for a flexible clock interface.

The Cadence IP provides matching dual channels for communication systems where these are desired, simplifying implementation and reducing risk, and a standard CMOS process target for easy manufacturing.

The data converter IP cores can be easily combined to form a complete analog front end (AFE) IP solution.

More info: Cadence Family of Analog IP