Real Intent introduced the latest version of Ascent X-Verification System (XV) tool for early functional analysis of digital designs. The new version features enhancements for initialization analysis, and the detection and management of unknown logic values (X’s). The latest version of Ascent XV is available now for download.
Ascent XV Features
- Initialization analysis that reports flops and latches uninitialized after the reset sequence
- Reset and retention-flop optimization that ensures complete initialization with minimal hardware and routing requirements for savings in area and power
- Hazard analysis that reports design susceptibility to X-hazards, and automatically detects and reports all X-sources in the design
- SimPortal that enables Verilog simulation to detect and debug real X-optimism issues, and to model low power retention cells at RTL
- A debugger that correlates X-optimistic and X-pessimistic signals to X-sources
Ascent X-Design and Verification System identifies X-sources and potential X-propagation issues early-on in Verilog RTL or netlist designs. The tool enables the detection and debug of functional issues caused by X-optimism at RTL, prior to synthesis. It also eliminates unnecessary X’s caused by X-pessimism at the netlist. Ascent XV analysis can catch issues prior to RTL sign-off, driving costs down and avoiding monotonous, error-prone debug at the netlist level.
More info: Real Intent Ascent XV