Synopsys Debuts DesignWare HDMI 2.0 TX/RX IP Solutions

Synopsys DesignWare HDMI 2.0 TX/RX IP solutions

Synopsys introduced their DesignWare HDMI 2.0 TX/RX IP solutions. The DesignWare HDMI 2.0 IP solution includes controller, PHY, and example Linux drivers. The solution reduce designers’ integration risk and time-to-market. The DesignWare HDMI 2.0 RX/TX Controller and PHY IP are available now in 28-nm process nodes from multiple foundries.

Synopsys DesignWare HDMI 2.0 RX/TX Controller and PHY IP Features

  • New DesignWare HDMI 2.0 IP provides 18 Gbps aggregate bandwidth in deep color mode
  • Supports ultra high-definition 4K x 2K resolution at 60 Hz frame rate
  • Supports all HDMI 2.0 specification features, including YCbCr 4:2:0 color space, TMDS scrambling
  • Reduces EMI and CEC 2.0 for advanced remote control units
  • Robust analog front end supports 100+ foot long cables with 5-V tolerant I/Os
  • Complete set of software drivers for Linux platform can reduce designers’ software development effort from weeks to hours
  • 28nm PHY architecture offers 33 percent lower power and 25 percent smaller area compared to previous generation

The DesignWare HDMI 2.0 IP features an aggregate bandwidth of up to 18 Gbps. It enables 4K x 2K (4400 vertical pixels x 2250 horizontal pixels) resolution at a 60 Hz frame rate in deep color mode to provide a flickerless, ultra high-definition (UHD) viewing experience. The IP’s ability to scramble transition-minimized differential signaling (TMDS) data above 3.4 Gbps adds to the high-quality viewing experience by minimizing the electromagnetic interference (EMI) that occurs in 8b/10b coded data streams. In addition, its robust analog front end supports pre-emphasis and adaptive equalization for excellent signal integrity across cables lengths of greater than 100 feet.

The DesignWare HDMI 2.0 IP solution offers a modular, flexible design that is optimized for area, power, pin count and gate count to reduce die size and bill-of-material (BOM) costs in HDTV system-on-chips (SoCs). The solution’s configurability enables designers to future-proof their HDTV SoCs by supporting functional updates in software. The 28-nanometer (nm) HDMI 2.0 PHY offers 33% lower active and leakage power consumption than the previous generation to help comply with Energy Star requirements. In addition, the single PLL architecture and optimized I/O ring reduce silicon area by 25% compared to the previous generation. The HDMI 2.0 PHY can achieve 6 Gbps performance in a wirebond package, and the pin order can support a two-layer PCB board for BOM cost savings.

To assist in software development, Synopsys provides HDMI 2.0 drivers in the Linux kernel. The software drivers, which include high-bandwidth digital content protection (HDCP), extended display identification data (EDID) and consumer electronics control (CEC) functionality, can reduce designers’ software development time from weeks to hours.

More info: Synopsys DesignWare IP