Cadence Design Systems released new verification IP (VIP) models for the latest memory standards: LPDDR4, Wide I/O 2, eMMC 5.0, HMC and DDR4 LRDIMM. LPDDR4 and Wide I/O 2 are key new standards for memory interfaces, and the availability of memory models will help designers to take advantage of the new standards quickly.
Advanced features of the Cadence new models include trace debug, address scrambling and backdoor memory access. In addition, the models support all leading third party simulators, verification languages and methodologies. This enables SoC designers to verify the correctness of interfaces to these new, specialized memories.
According to Cadence, designers are faced with more standards being introduced but with shorter lifecycles. At the same time, they need to address power, performance, cost, thermal and packaging constraints. To address this, Cadence is providing access to models supporting as many standards options as possible. This helps designers can get to market success as fast as possible.
More info: Cadence Design Systems