Synopsys Introduces DesignWare Sensor IP Subsystem

Synopsys DesignWare Sensor IP Subsystem

Synopsys introduced their DesignWare Sensor IP Subsystem, which is a complete and integrated hardware and software solution for sensor control applications. The DesignWare Sensor IP Subsystem reduces integration effort and cost. The Synopsys DesignWare Sensor IP Subsystem is expected to be available in October of this year to early adopters. General availability is planned for the fourth quarter of 2013.

Synopsys DesignWare Sensor IP Subsystem block diagram

Synopsys DesignWare Sensor IP Subsystem Features

  • Integrated, pre-verified hardware and software IP subsystem
  • Consists of a power- and area-efficient ARC 32-bit processor, digital and analog interfaces, hardware accelerators, software library of DSP functions and I/O drivers
  • Highly configurable with tightly integrated peripherals and dedicated hardware maximize sensor processing efficiency
  • More than ten configurable hardware accelerators reduce memory footprint
  • Decreases power consumption by a factor of 10 compared to equivalent discrete component implementations
  • Extensive library of off-the-shelf software DSP functions, including mathematical, filtering, matrix/vector and decimation/interpolation, speeds application software development
  • Implementations as small as 0.01mm2, consuming less than 4uW/MHz in a 28nm process

The new IP subsystem is optimized to process data from digital and analog sensors, offloading the host processor and enabling more efficient processing of the sensor data with ultra-low power. The fully configurable subsystem consists of a DesignWare ARC EM4 32-bit processor, digital interfaces, analog-to-digital data converters (ADCs), hardware accelerators, a comprehensive software library of DSP functions and software I/O drivers. The DesignWare Sensor IP Subsystem provides designers with a complete and pre-verified solution that meets the requirements of a broad range of applications such as smart sensors, sensor fusion and sensor hub.

The DesignWare Sensor IP Subsystem features the power- and area-efficient DesignWare ARC EM4 32-bit processor core, which includes custom extensions and instructions that support application-specific hardware accelerators and tightly integrated peripherals. The subsystem includes multiple configurable GPIO, SPI and I2C digital interfaces for off-chip sensor connections as well as ARM AMBA AHB and APB protocol system interfaces to ease integration into the full SoC. The analog interfaces include low-power high-resolution ADCs that efficiently digitize sensor data for the processor. The sensor subsystem’s HAPS FPGA-based prototyping solution enables immediate software development and provides a scalable platform for rapid full system integration and validation.

The DesignWare Sensor IP Subsystem offers a rich library of DSP functions, including mathematical, complex math, filtering (FIR, IIR, correlation, etc.), matrix/vector and decimation/interpolation that help accelerate sensor application code development. In addition, peripheral software drivers are provided to ease integration of the I/O with the ARC EM4 processor, and host drivers are provided to interface the DesignWare Sensor IP Subsystem to the host processor.

More info: Synopsys DesignWare Sensor IP Subsystem Datasheet (pdf)