Cadence Design Systems announced their Virtuoso Layout Suite for Electrically Aware Design (EAD). The tool for automating custom design enables layout designers and circuit designers to work together more efficiently and effectively through greater real-time visibility into electrical issues. Cadence Virtuoso Layout Suite EAD helps engineers to reduce circuit design cycle by up to 30% while optimizing chip size and performance.
Cadence Virtuoso Layout Suite EAD Features
- Performs real-time analysis and optimization
- Built-in interconnect parasitic extraction engine that instantly evaluates layout as it is created
- Enables engineers to set electrical constraints and observe, in real time, whether these constraints are being met
- Alerts designers to electromigration issues that are created as layout is drawn
- Minimizes respins and over design via partial layout resimulation of existing interconnect parasitics
- Reduces circuit design cycle by up to 30%
- Enables engineers to optimize chip performance and utilize less area
The tool’s in-design electrical verification capability enables design teams to monitor electrical issues while a layout is created, rather than wait until the layout is completed before verifying that it meets the original design intent.
Engineers can electrically analyze, simulate and verify interconnect decisions in real time. This results in layout that is electrically correct-by-construction. The real-time visibility lets engineers reduce conservative design practices — or over-design — that can negatively impact a chip’s performance and area.
More info: Cadence Virtuoso Layout Suite for Electrically Aware Design (pdf)