Cadence Design Systems recently introduced their PCIe Controller and PHY solution. The new design IP is ideal for low-power PCI Express (PCIe) development. The PCIe 3.0 controllers and PHY will help designers reduce leakage power consumed by the PCIe interface from milliWatts to microWatts. The solution is ideal for datacenter and enterprise applications.
Cadence PCIe 3.0 PHY Highlights
- Circuit calibration technique enables designers to meet aggressive active power goals
- Advanced power and clock management capabilities reduce standby current by 100X
- Optimized transition time latency between active and sleep states
The new Cadence PCIe Controller and PHY solution enables engineers to meet design goals for active and standby power and exit latency through innovations in circuit calibration, power and clock management, and PLL technology.
The new Cadence PCIe IP supports x16 configuration. This gives designers the maximum performance along with virtualization support to service multi-threaded applications. With the additional support of the latest low-power PCIe L1 PM Substrates Engineering Change Notice (ECN) across all Cadence PCIe IP, Cadence is able to provide both low power and high performance during peak operation and system power savings during idle operation.
The Cadence PCIe 3.0 PHY provides flexible lane support and the ability to support wire bond for mobile, client and cost-sensitive applications, and flip chip for enterprise and high performance systems. Cadence also recently announced its M-PCIe controller targeted for low-power mobile applications.
More info: Cadence Design IP