Real Intent Launches Meridian CDC 5.0 Analysis Tool

Real Intent launched version five of their Meridian CDC tool. The new hierarchical CDC flow supports partitioned analysis of designs without sacrificing top-level full-chip precision for giga-scale sign-off. Meridian CDC’s hierarchical flow avoids the compromises found with abstract-modeling and the use of waivers in other products. Meridian CDC v5.0 will be available July 1, 2013. Pricing depends on product configuration.

Meridian CDC Version 5.0 Features

  • A hierarchical flow that supports partitioned analysis of designs without waivers or sacrifice of top-level full-chip precision to achieve sign-off of giga-scale designs
  • A new correct-by-configuration design setup to enhance analysis and reporting clarity for clock crossings to ease the sign-off process
  • Enriched SDC design constraint support with the addition of set clock groups and naming schemes
  • “Cleaner and meaner” issue reporting for: bus handling; reset analysis, including glitches in both asynchronous and synchronous domains; and crossings that may be blocked by environment definition
  • An enhanced formal analysis engine with greater speed and coverage
  • Significant enhancements to the SystemVerilog support for interface elements
  • Verdi3 integration — the industry-leading debug platform from Synopsys (formerly SpringSoft)

Real Intent Meridian CDC v5 clock domain crossing analysis software includes enhanced speed, analysis and SystemVerilog language support.

Meridian CDC performs comprehensive structural and functional analysis to ensure that signals crossing asynchronous clock domains on ASIC or FPGA devices are received reliably. With a giga-scale capacity, Meridian CDC is the only solution that enables all aspects of CDC sign-off. Meridian CDC excels in speed and low-noise analysis of asynchronous clock domains in SoC designs, with an enhanced formal engine that now goes even further and faster to find hidden CDC problems.

The clock domain crossing analysis tool’s design language support now includes the SystemVerilog synthesizable subset. In addition, Real Intent has enhanced the user experience with a new front-end interface that incorporates the latest Verdi Automated Debug System from Synopsys, and delivers improved analysis setup, debug features and ease of use.

More info: Real Intent Meridian CDC

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