Synopsys Optimizes DesignWare HPC Design Kit for All SoC Processor Cores

Synopsys DesignWare High Performance Core (HPC) Design Kit

Synopsys has extended their DesignWare Duet Embedded Memory and Logic Library IP to enable the optimized implementation of a broad range of processor cores. In one package, designers now have access to the specialty cells and memories they need to optimize their CPU, GPU and DSP cores across the full speed, power and area spectrum. The DesignWare HPC Design Kit will be available for leading 28-nm processes starting in July of this year.

Synopsys DesignWare High Performance Core Design Kit

  • One design kit for optimizing all processor cores on an SoC that includes an ultra-high density memory compiler and more than 125 new standard cells and memory instances
  • Delivers up to 10 percent performance improvement on host CPU cores and up to 25% lower power with 10% area reduction on GPU cores such as the Imagination Technology PowerVR Series6 IP core
  • Developed in close collaboration with key partners including Imagination Technologies, CEVA and VeriSilicon
  • Implement your optimized processor cores in as little as four to six weeks with Synopsys FastOpt services

The new DesignWare HPC (High Performance Core) Design Kit contains a suite of high-speed and high-density memory instances and standard cell libraries that allow system-on-chip (SoC) designers to optimize their on-chip CPU, GPU and DSP IP cores for maximum speed, smallest area or lowest power — or to achieve an optimum balance of the three for their specific application.

The HPC Design Kit contains fast cache memory instances and performance-tuned flip-flops that enable speed improvement of up to 10% over the standard Duet package. To minimize dynamic and leakage power as well as die area, the new kit provides area-optimized and multi-bit flip-flops and an ultra-high-density two-port SRAM, delivering demonstrated reductions in area and power of up to 25% while maintaining processor performance.

Synopsys’ broad portfolio of DesignWare IP includes silicon-proven embedded memory compilers and standard cell libraries that support a range of foundries and processes from 180 to 28 nanometers (nm) and have shipped in more than three billion chips. The DesignWare Duet Package of Embedded Memories and Logic Libraries contains all the physical IP elements needed to implement a complete SoC including standard cells, SRAM compilers, register files, ROMs, datapath libraries and Power Optimization Kits (POKs).

Options for overdrive/low- voltage process, voltage and temperature (PVT) corners, multi-channel cells, and memory built-in self-test (BIST) and repair are also available. The DesignWare HPC Design Kit adds performance-, power- and area-optimized standard cells and memory instances tuned for the special speed and density requirements of advanced CPU, GPU and DSP cores.

More info: Synopsys DesignWare High Performance Core (HPC) Design Kit