Synopsys has developed a new test technology to further reduce the cost of testing silicon devices by delivering up to 3x higher test compression and minimizing the time required to test each silicon die. The new test technology is embedded in Synopsys’ Design Compiler RTL synthesis and TetraMAX ATPG solutions. Synopsys’ synthesis-based test innovation will help engineers meet more stringent test cost and quality goals within tighter design schedules.
The new technology uses fewer pins and higher-frequency on-chip design-for-test (DFT) circuitry. This enables design teams to test several die in parallel and use the maximum performance of their tester equipment to achieve additional reduction in test time and cost.
Synopsys’ new test technology shows it can achieve up to three times higher compression compared to existing solutions. The technology can be deployed on a variety of design styles with any number of test pins and supports high-speed test clocks.
Synopsys’ new synthesis-based test technology uses an innovative method to efficiently stream compressed test data in and out of the DFT circuitry. This significantly reduces the amount of data required to achieve high test quality. This method requires fewer test pins and enables silicon parts to operate at higher frequencies while in test mode. As a result, more die can be tested in parallel, and the time required to test each die is further reduced.
More info: Synopsys, Inc.