Mentor Graphics has added cache coherent interconnect subsystem verification to the Questa and Veloce platforms. ARM AMBA 5 CHI and AMBA 4 ACE specifications enable high performance, coherent SoC design functionality to be at the heart of the Questa and Veloce platforms. The Questa and Veloce platform AMBA 4 ACE verification solutions are available now. The AMBA 5 CHI verification solutions are available to approved ARM AMBA 5 CHI licensees.
Engineering teams designing high-performance, distributed computing systems with ARM’s AMBA 5 CHI specification, or mobile applications devices with ARM’s AMBA 4 ACE specification, can now fully verify that the interconnect subsystems achieve maximum system-level performance and the distributed cache memories are coherent.
Engineering teams designing SoCs with ARM’s AMBA 5 CHI specification or AMBA 4 ACE specification want their products to achieve maximum performance with minimum power consumption. The Mentor new multi-core, cache-coherent verification solution enables engineers to ensure that system-level designs are optimized to take the fullest advantage of either architecture. It confirms system-level protocol adherence and efficient cache coherency, as well as interconnect dynamic connectivity and performance.