Cadence Design Systems announced the Tempus Timing Signoff Solution. The Tempus static timing analysis and closure tool enables System-on-Chip (SoC) developers to speed timing closure and move chip designs to fabrication quickly. The Cadence Tempus Timing Signoff Solution is expected to be available in the third quarter of 2013.
Tempus Timing Signoff Solution Features
- First massively distributed parallel timing engine on the market which can scale to utilize up to hundreds of CPUs
- Parallel architecture enables the Tempus Timing Signoff Solution to analyze designs in the hundreds of millions of instances without compromising accuracy
- A new path-based analysis engine that leverages multi-core processing to reduce pessimism
- Enables broader use of path-based analysis than other solutions
- Multi-mode, multi-corner (MMMC) analysis and physically-aware timing closure that leverages multi-threaded and distributed timing analysis
The Tempus Timing Signoff Solution represents a significant advancement in timing signoff tool innovation and performance. It leverages multi-processing and ECO features to achieve signoff faster than with traditional flows. The solution enables engineers to shrink timing signoff closure and analysis for faster tapeout while producing designs with less pessimism, area and power consumption.
Cadence’s Tempus Timing Signoff Solution advanced capabilities can handle designs containing hundreds of millions of cell instances without compromising accuracy. Initial engagements with customers have shown that the Tempus Timing Signoff Solution can achieve timing closure in days on a design that would have taken several weeks with traditional flows.
More info: Tempus Timing Signoff Solution