Synopsys IC Compiler 2013.03 Speeds Design Closure

Synopsys recently released a new version of their IC Compiler software. Release 2013.03 features innovations to speed design as well as enables the latest process nodes. IC Compiler 2013.03 includes advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.

New features of IC Compiler software include advanced optimizations to enable high-speed design, efficient implementation of final-stage engineering change orders (ECO) and fully color-ready, tapeout-proven support for the emerging FinFET-based silicon processes.

The IC Compiler 2013.03 enables even faster design closure. IC Compiler, working hand-in-hand with Synopsys’ PrimeTime signoff solution, provides a highly efficient ECO solution rooted in dual principles. IC Compiler ensures that very few ECOs are required after the optimization steps. In addition, the tool applies the ECOs surgically with minimal layout perturbation. In this flow, PrimeTime provides signoff-accurate ECO guidance, implemented using the new minimum physical impact ECO capability, which greatly reduces layout perturbation by reusing wires and minimizing device displacement. Combined with a fully automatic, incremental In-Design physical verification capability, IC Compiler provides a significant reduction in turnaround time for ECO closure.

The Synopsys 2013.03 IC Compiler release enables high-speed clock design by performing clock estimation during placement to drive physical- and timing-aware clock gating concurrently with clock and data optimization to achieve the target frequency faster.

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