Cadence Design Systems Debuts Incisive Enterprise Simulator v13.1

Cadence Incisive Enterprise Simulator screenshot

Cadence Design Systems released version 13.1 of the Incisive Enterprise Simulator. The latest release of the software tool improves low-power verification productivity of complex SoCs by 30%. Cadence Incisive Enterprise Simulator v13.1 features new capabilities that ease the challenge of verifying all of today’s power-aware designs.

Cadence Incisive Enterprise Simulator block diagram

The new version of Incisive Enterprise Simulator addresses low-power verification challenges for advanced modeling, debug, power format support and to provide faster verification for today’s most complex SoCs.

The new debug features in Incisive SimVision Debugger provide simple visualization and interactive debug of both complex text-based power intent standards. Other simulator enhancements include additional SystemVerilog support and faster elaboration to turn around simulation jobs much more quickly. Enhanced support for CPF and newly added support of IEEE 1801 will make these enhancements available to all low-power engineers.

Cadence Incisive Enterprise Simulator Features

  • Fuels testbench automation, analysis, and reuse for increased productivity
  • Ensures verification quality by tracking industry-standard coverage metrics including functional, transactional, low-power, and HDL code, plus automatic data and assertion checking
  • Drives and guides verification with an automatically back-annotated and executable verification plan
  • Creates reusable sequences and multi-channel virtual sequences on top of a multi-language verification environment
  • Configures existing Universal Verification Components (UVCs) or quickly constructs all-new UVCs
  • Enables advanced debug using SimVision for transaction-level models, SystemVerilog/e class libraries, and transient mixed-signal, low-power, and traditional waveform analysis
  • Supports e, Open Verification Library (OVL), OVM class library, UVM class library, SystemC, SystemC Verification Library, SystemVerilog, Verilog, VHDL, PSL, SVA, and CPF
  • Delivers the highest possible performance across multiple levels of abstraction, supporting the ability to hot swap the RTL simulation in/out of the Palladium XP accelerator/emulator

More info: Cadence Incisive Enterprise Simulator (pdf)

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