Synopsys Embedded Vision Development System Reduces Bring-up Time by Months

Synopsys Embedded Vision Development System

Synopsys introduced the Embedded Vision Development System. The new Synopsys is an integrated solution for the acceleration of the design of processors for embedded vision. It is based on Synopsys’ Processor Designer tool set and Synopsys’ HAPS FPGA-based prototyping system. The Embedded Vision Development System is immediately available now.

Synopsys Embedded Vision Development System Features

  • Design embedded vision processor
  • Tailor to specific power and performance requirements
  • Explore and tune new processor architectures in hours instead of weeks
  • Reduce system bring-up time by months
  • Pre-validated embedded vision reference flows for HAPS FPGA-based prototypes
  • Combines Synopsys Processor Designer and HAPS FPGA prototyping system

The Embedded Vision Development System enables engineers to quickly explore and tune processor architectures for the optimal combination of power and speed, and rapidly implement the design on a HAPS FPGA-based prototype.

The new Synopsys Embedded Vision Development System includes pre-verified design examples to help designers quickly implement an ASIP optimized to meet specific SoC objectives for power consumption and performance. It provides a ready-to-use, modifiable base processor including a full C/C++ compiler, which supports all functions provided by the OpenCV library.

The execution of the compiled code with the automatically-generated instruction-set simulator (ISS) is easy to profile, clearly identifying performance-intensive parts of the application, which can be accelerated by changes in the processor architecture, including memory access, register configuration and instruction set. Unlike configurable processors that rely on a fixed pipeline and register structure, this methodology removes limitations from achieving the most power- and performance-optimized custom architecture for their application. Using the automatically generated software tools, designers easily recompile and simulate the C/C++ program until they achieve their design goals.

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