Mentor Graphics Debuts IP to System, UPF Low-power Verification Flow

Mentor Graphics introduced a comprehensive IP to System, UPF-based low-power verification flow. Mentor now has platform-level support of Unified Power Format in both the Questa functional verification platform and the Veloce family of hardware emulators that lets users create a single specification for power intent that is reusable and consistent, and facilitates low-power verification across simulation, formal and emulation.

The IEEE-1801 UPF has emerged as the low- power standard that enables designers to specify a design’s power intent separately from the design itself ensuring reuse, portability and greater flexibility in power management techniques.

Questa increases UPF simulation performance by a factor of six. This provides the power to verify the integration of a subsystem or full chip with its power management architecture. This performance, combined with the new power intent visibility in the Questa GUI and automatic low-power checks, enables designers to easily and completely verify, visualize and debug all effects of adding the UPF to both RTL and gate level simulations.

The Questa functional verification platform also includes new automatic low-power coverage metrics and the generation of a low-power test plan. This makes it easy to include power management coverage points to a comprehensive coverage closure strategy. The new release improves support and compatibility for the open Liberty library format, which provides a smooth flow between low-power synthesis and implementation.

Questa CDC now reads the Unified Power Format to automatically detect errors injected by additional logic introduced by UPF. This ensures low-power clock domain crossing verification. Clock domain crossing verification has become critical to detect clock interaction issues that cannot be detected in simulation-based techniques.

The Veloce emulator now delivers the most comprehensive UPF support for low-power emulation. It also automatically synthesizes the UPF power intent logic and performs dynamic checks for monitoring low-power functionality, alerting users to cases of incorrect low-power behavior. Veloce now makes it possible to run application-level software in power critical scenarios.

More info: Mentor Graphics Corporation