ProPlus Design Solutions introduced NanoSpice. The tool is a next-generation high-capacity, high-performance parallel SPICE simulator for giga-scale circuit simulation. NanoSpice enables giga-scale simulation and for handling process variations from 3-sigma to high-sigma Monte Carlo simulations with full matrix solving and without approximations in model calculations. ProPlus NanoSpice is shipping now.
NanoSpice is a pure SPICE circuit simulator. It shares the same core SPICE engine with ProPlus’ BSIMProPlus, which is the de-facto golden device modeling software used by all leading foundries. The tool has built-in foundry-validated accuracy and compatibility. It has full SPICE analysis features and supports industry-standard inputs and outputs.
The new parallel SPICE simulator uses effective model-handling and high-performance parallelization technology with high memory efficiency. NanoSpice runs 10 to more than 100 times faster than traditional SPICE simulators. It is able to handle all circuit types, with an ability to simulate large-scale circuits of 50-million or more elements for generic circuit types, and 100-million or more elements for memory circuits.
The ProPlus tool is ideal for memory, analog/mixed-signal, I/O, custom digital and standard cell design. NanoSpice handles challenging designs, including the characterization of large embedded SRAM blocks, post-layout analysis of analog circuits, sign-off simulation of full-chip power integrated circuit (IC) or wireless transceiver circuits, and accurate clock tree and critical path analysis.
NanoSpice is tightly integrated with ProPlus’ DFY platform NanoYield for variation analysis with efficient process, voltage and temperature (PVT) corner sampling, fast Monte Carlo or silicon-proven, high-sigma sampling with technology licensed from IBM.
ProPlus NanoSpice Parallel SPICE Simulator Features
- Supports industry standard netlist formats: HSPICE, Spectre
- Supports standard output formats for data analysis: FSDB, ASCII, PSFASCII
- Rich analysis features including DC Operating Point, DC Bias Point and DC Sweep Analysis
- AC Bias Point and AC Frequency Sweep Analysis, Transient Bias Point and Sweep Analysis, Noise, Transient Noise, Info, Sweep, ALTER, Monte Carlo
- Fully supports Verilog-A and behavioral sources
- Supports Verilog co-simulation
- Supports SPEF back-annotation
- Integrated with Cadence Analog Design Environment
- Easy-to-use command line with no complicated options or special syntax
More info: ProPlus NanoSpice Parallel SPICE Simulator