CDNLive Silicon Valley User Conference to Take Place in March

CDNLive Silicon Valley User Conference

Cadence Design Systems will hold their CDNLive Silicon Valley User Conference on March 12 and 13 in Santa Clara. CDNLive Silicon Valley brings together Cadence technology users, developers, and industry experts to network, share best practices on critical design and verification issues, and discover new techniques for realizing advanced silicon, SoCs, and systems.

2013 CDN Live Topics

  • Physical Aware Synthesis Challenges in Flash Memory Design
  • Data Management for Mixed-Signal Designs
  • CSR Automated Routing of Complex Digital Custom Blocks
  • Improve Debug Productivity from Hours to Minutes Using the Incisive Debug Analyzer
  • System to Silicon Verification – How It All Fits Together
  • DDR4 System Design Challenges
  • High Performance/Low Power Implementation of ARM Cortex-A15 and Cortex-A7 with ARM POP IP for ARM big.LITTLE Systems and Applications
  • Conformal LEC Script Throughput Minimizer
  • A Method for Analog Interface Signal Coverage Checking in Analog IP Design
  • Case Study: Enabling an Antifuse Memory IP Block on 20nm Process
  • UVM-e Based Validation IP re-use for Emulation
  • Case Study: Using Cadence Palladium for SoC Performance Validation and Analysis
  • Non-Volatile Design Verification Challenges
  • Advanced Strategies for Timing Closure Utilizing New GigaOpt Features
  • Planning for Conformal ECO Early in the Design Cycle
  • Productivity Driven Analog Mixed Signal Design Methodology in Advanced Node Microprocessor Design
  • Improving Productivity with Electrically Aware Design Solutions
  • Are you Still Building Test Benches?
  • A High-Level Synthesis Technology Using C Source Code Analysis
  • Is SSIC (Super-Speed Interconnect) – Revolutionizing the Mobile Design?
  • Targeting High Frequency and Power Efficient Implementations for ARM’s High Performance Cortex-A57 Processor
  • “Herding cats” Keeping Your SDC Code Sane in a Multi-tool Environment
  • APS Electromigration and IR Drop Analysis of Mixed Signal Circuits
  • The Hierarchical Approach For Full-chip Flash Memory Array Static ERC
  • Advances in Client-Server Technology for More Verification Automation
  • Enabling a New Paradigm of System-level Debug Productivity While Maintaining Full In-circuit Emulation Performance
  • Using Virtual Platforms for Firmware Verification
  • Implementing High Performance GHz+ Mobile Applications Processors and GPU with Clock Concurrent Design Techniques
  • A Scalable, Programmable Memory BIST Solution for Your Needs Today – and Tomorrow
  • Jitter and Duty Cycle Measurement Technique for Analog Full Custom Cells Using AMS Tools
  • Constraint Manager/PVS-CV Driven Flow
  • Model Driven ARM ACE Test Scenario Generator
  • Analyzing and Debugging Performance Issues with Complex ARM CoreLink System IP Components
  • X-Gene: Realizing a Complex High-performance and Power Efficient 64-bit Multicore ARMv8 Based Server-on-Chip Solution in Silicon

CDN Live Worldwide Series of User Conferences

  • Munich, Germany – May 6-8
  • Hsinchu, Taiwan – July 11
  • Seoul, Korea – July 16
  • Yokohama, Japan – July 19
  • Boston, USA – Aug. 27
  • Beijing, China – Sept. 10
  • Shanghai, China – Sept. 12
  • Bangalore, India – Oct. 9
  • Tel Aviv, Israel – Oct. 14

More info: CDNLive Silicon Valley 2013