Tensilica Debuts Imaging and Video Dataplane Processor

Tensilica announced their imaging and video dataplane processor. The IVP DSP architecture supports very high-quality image and video capture using advanced single-frame and multi-frame processing. The IP core supports increasing sensor resolutions. The IVP DPU is available for broad licensing now. The core is ideal for the complex image/video signal processing functions in mobile handsets, tablets, digital televisions (DTV), automotive, video games and computer vision based applications.

The IVP DPU enables applications never before possible in a programmable device. The Tensilica IP core is supported by a network of third-party application developers who are actively porting leading-edge image applications to the IVP platform including innovative multi-frame image capture and video pre- and post-processing algorithms, as well as established yet evolving technologies such as video stabilization, high dynamic range (HDR) image, video HDR, object and face recognition and tracking, low-light image enhancement, digital zoom and gesture recognition.

The Tensilica IVP DSP has a unique instruction set tuned for imaging and video pixel processing that gives it an instruction throughput of over 16x the number of 16-bit pixel operations compared to that of the typical host CPU with single-issue vector instructions. In addition to its raw instruction throughput advantage to host CPUs, the imaging specific compound instructions supported by IVP give it a higher peak performance of 10 to 20x and much higher energy efficiency. IVP’s instruction set has over 300 imaging, video and vision-oriented vector operations, each of which applies to 32 or more 16-bit pixels per cycle.

The new IP core is based on a four-way VLIW (very long instruction word) architecture that features high parallelism intermixed with code-compact instructions, with a 32-way vector SIMD (single instruction, multiple data) dataset. The architecture includes an integrated DMA (direct memory access) transfer engine with up to 10 GBytes/second of throughput and local memory throughput of 1024 bits per cycle (sixty-four 16-bit pixels/cycle) to keep up with the rapid pace of resolution and frame rate requirements. The IVP also features many imaging-specific operations to accelerate 8-, 16- and 32-bit pixel data types and video operation patterns.

More info: Tensilica, Inc.