Cadence Virtuoso Advanced Node Targets for 20nm Design

Cadence Design Systems Virtuoso Advanced Node for 20nm Design

Cadence Design Systems introduced Virtuoso Advanced Node, which is a set of custom/analog capabilities designed for the advanced technology nodes of 20 nanometers and below. Virtuoso Advanced Node enables design teams to optimize designs for performance, power and area while reducing or even eliminating tasks that would make 20nm design much more time consuming and labor intensive.

Cadence Virtuoso Advanced Node prevent errors before they are created rather than detect them late in the design process. Working in concert with Cadence Encounter RTL-to-GDSII flow, QRC Extraction and Physical Verification System, Virtuoso Advanced Node enables the development of complex mixed-signal chips that power today’s leading consumer electronics devices.

Cadence Virtuoso Advanced Node Features

  • LDE analysis using incremental layout
    Virtuoso Advanced Node enables engineers to build their physical design and check it as they go, to ensure they are making the right choice at each step, rather than having to wait until the end. It delivers novel technology that helps decrease costly design iterations by allowing designers the ability to use partially completed layout as part of the LDE analysis, detecting layout-dependent effects at the earliest moment in the design cycle. LDEs are handled with detailed test benches that analyze multiple corners to ensure that the circuit will function as specified.

  • Double patterning and color-aware layout
    Double patterning splits the design layers into two masks, separating structures that are too close together. But double patterning brings coloring challenges to designers. Virtuoso Advanced Node delivers real-time automated color-aware, design-rule-driven layout to enable the creation of area-optimized layout. It provides engineers the ability to match, lock and store colors on critical nets and geometries (through schematic constraints or directly on the layout), and to identify, debug and fix errors as they go, rather than later in the design process, when they are more difficult to fix.

  • New routing layers
    Foundries require the utilization of new local interconnect (LI) layers, or middle-of-line (MOL) layers, that are used to create densely packed routes inside complex devices. These layers have restricted design rules governing local interconnect and the vias that are used with them, presenting the challenge of maintaining signal integrity from pin to pin of the transistors. Virtuoso Advanced Node technology provides a local interconnect-aware wire editor and router that address the issue of complex LI rules.

More info: Cadence Design Systems

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