Cadence Design Systems released version 12.2 of their Incisive functional verification platform and methodologies. Cadence Incisive v12.2 provides the productivity improvements the engineering teams need to bring their designs to market fast and at high quality. The tool features a broad set of new and enhanced capabilities that double the productivity of SoC verification over the previous version.
The new Incisive release features 2x performance, a new Incisive Debug Analyzer product, new low-power modeling, and hundreds of additional features needed to perform effective verification of today’s complex intellectual property (IP) and SoCs.
Incisive v12.2 integrates with Cadence verification IP for SoC verification, the Cadence Virtual System Platform for system verification, and the Palladium XP for acceleration which includes the ability to hot-swap between software-based simulation and hardware-based acceleration.
IP Block-to-chip Verification Enhancements
- Doubled performance from the simulator engine
- Improved debug capabilities with the recently introduced Incisive Debug Analyzer
- Automated Register Validation App that replaces hundreds of functional tests with a single formal analysis run
- Simplified coverage data analysis with the new Incisive Metrics Center feature
SoC Verification Enhancements
- An enhanced low-power algorithm in the simulator that delivers a 2x improvement in elaboration time. The new Incisive technology accurately models shutdown and recovery in low-power designs
- An integrated digital-centric mixed-signal solution that uses real number models (RNM), resulting in simulation speed increases of over 300x using wreal or SystemVerilog-RNM types
- Accelerated block and toggle coverage supported in Palladium XP Simulation Acceleration, reducing test time from hours to minutes
More info: Cadence Design Systems, Inc.