Ascent Lint 2.0 Features 60 New Rules, Enhanced SystemVerilog Support
Real Intent launched Ascent Lint 2.0 RTL linter and design rule checker for full-chip SoC analysis. The latest version of the tool includes 60 additional rules — including new FSM checks. It features analysis speed of 450M gates in less than one hour, with no need for hierarchical processing. Ascent Lint 2.0 is available now for download. The tool is ideal for early functional verification.
Ascent Lint 2.0 supports the Verdi3 debug platform from Synopsys (formerly SpringSoft). This new release maintains Real Intent’s product leadership in delivering what the company believes is the industry’s best-in-class RTL linter and design rule checker for full-chip SoC analysis.
IDT’s comprehensive design rule-set is fully supported and it only takes a few minutes for runs to complete. The tool is easy to use and debug is fast and efficient.
Ascent Lint 2.0 offers enhanced support for SystemVerilog, Verilog and VHDL languages. The tool improves ease of use in the GUI and low-noise reporting of design issues. The expanded rule set ensures design code quality and consistency for a wide range of potential issues.
Ascent Lint 2.0 Expanded Rule Set Highlights
- New FSM modeling checks and coding conventions
- Expanded checking of unsynthesizable constructs
- Coding that leads to functional errors or simulation-synthesis mismatches
- Mixing of different hardware description languages
More info: Real Intent RTL Lint Analyzer and Rule Checker (pdf)
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