SynaptiCAD Timing Diagram Editors Support Synopsys Design Constraint Files

SynaptiCAD has released new versions of their timing diagram editing tools that can create and edit Synopsys Design Constraint (SDC) files using data from timing diagrams. This capability makes creation of SDC files quicker and less error prone and also gives designers the ability to visualize the timing constraints.

SynaptiCAD’s timing diagram editors currently support rapid graphical creation of the most commonly used timing constraint commands including: create_clock, create_generated_clock, set_input_delay, set_output_delay, set_min_delay, set_max_delay, and set_false_path. A few clicks enable these commands to be automatically generated and updated from the delays, setups, holds, and clocks in your timing diagram.

Engineers with an advanced version of SynaptiCAD’s timing diagram editors that supports project management (WaveFormer Pro with Reactive Test Bench Generation, DataSheet Pro, VeriLogger Pro, or TestBencher Pro), can take advantage of additional SDC editing capabilities. A new SDC-aware text editor and the ability to link SDC commands between multiple SDC files enable multiple timing diagrams to feed timing constraint data to a common SDC file.

Included with the new version is a quick tutorial that walks you through the steps of generating an SDC file from a timing diagram.

More info: SynaptiCAD Tool Suite