Calypto Design Systems will host two webinars next month. The online seminars will educate designers on the latest in high level synthesis (HLS) and power optimization techniques for RTL-based designs. The titles of the webcasts are Minimizing RTL Power through Sequential Analysis, and A Practical Comparison Between C++ and SystemC for High Level Synthesis.
Minimizing RTL Power through Sequential Analysis will take place on Tuesday, December 4 at 11am PST. A Practical Comparison Between C++ and SystemC for High Level Synthesis will take place on Thursday, December 13 at 11am PST.
Minimizing RTL Power through Sequential Analysis Webinar
Analysing and optimizing power at RTL can significantly reduce power but is challenging especially when done manually. The widely used practice of inserting clock gating may not be very effective without considering the sequential nature of the design and representative switching activity. In this 50 minute webinar, Calypto will review the requirements for a comprehensive methodology to reduce power at the RTL level. The webcast will cover more advance topics such as how to analyze the RTL for wasted power and show optimization techniques to reduce power on real designs. The latest technique of sequential analyses will be described including stability based and the more difficult observability based sequential clock gating that provides maximum power optimization.
A Practical Comparison Between C++ and SystemC for High Level Synthesis Webinar
Have you ever wondered the difference between C++ and SystemC for high level synthesis (HLS)? This 50 minute webinar will provide a practical overview of the differences between the two most common ESL hardware description languages. The webinar will show side by side coding examples of the two languages for basic hardware concepts such as: hierarchy, IO, numerical precision and timing. As the only company to support both SystemC and C++ for synthesis with the industry’s most successful HLS tool (Catapult Synthesis), Calypto is uniquely placed to discuss the differences between the two languages. In this 50 minute webinar, we will cover the basics of designing for hardware with each language, covering what you can, and can’t do: bit-accurate datatypes, architecture design, interfacing, hierarchy, and verification.
More info: Calypto Design Systems Webinars