Synopsys introduced the latest version of their DesignWare STAR Memory System. The tool is an automated pre- and post-silicon memory test, debug, diagnostic and repair solution. The DesignWare Star Memory System enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield. The EDA tool is available now.
The new version of DesignWare STAR Memory System targets 20nm and FinFET-based designs. The tool features a new architecture for hierarchical implementation and validation of large SoC designs containing thousands of embedded memories. This can deduce the time required to implement tests while also decreasing area by up to 30%. In addition, the latest release efficiently addresses test and repair for new memory defects seen in 20nm processes and below (such as process variation faults and resistive faults).
The STAR Memory System architecture offers advanced memory addressing and programmable memory background patterns needed to create optimized test algorithms for detecting not only static and dynamic faults, but also process variation and resistive faults. In addition, the Synopsys tool also optimizes the test generation logic by storing only the unique test elements.
The Synopsys solution enables hierarchical generation and verification of the test and repair IP within the SoC while maintaining the original design hierarchy. This can speed up design and verification time while allowing reuse of existing design constraints and configuration files, reducing the overall SoC design time. The combination of these new features reduces total test and repair area by up to 30% compared to the previous generation product, while enabling faster design closure. These capabilities can also reduce the time required for silicon bring-up and defect analysis for yield optimization, enabling the ramp to volume production to occur in weeks rather than months.
More info: Synopsys DesignWare STAR Memory System